Method of filling gap with dielectrics

Details Method of filling gap with dielectrics Method of filling gap with dielectrics

1999-03-05

2001-05-29

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

C438S624000, C438S783000

Reexamination Certificate

active

06239024

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a semiconductor process. More particularly, the present invention relates to an improved method of filling gap with dielectrics.
2. Description of Related Art
With the increasing integration in integrated circuits (IC), a conventional wafer can no longer provide sufficient area for interconnects. In order to satisfy performance requirements, design rules of forming more than two metal layers for interconnects are gradually applied in integrated circuits. An inter-metal dielectric (IMD) layer is formed between two metal layers for isolation. Since a metal layer and a dielectric layer are alternately laminated to form metal interconnects, planarization and quality of the dielectric layer play an important role in semiconductor fabrication. If the result of the planarization is not ideal, the uneven surface of the dielectric layer causes misalignment when a subsequent photolithography process is performed so that the pattern cannot accurately transfer onto the metal line and the process becomes more difficult.
As device integration is increased, density of conductive lines is also increased. A gap is formed between every two neighboring conductive lines. While depositing a dielectric film of silicon oxide in a region with a high patterned density of the conductive lines, depositing rates on top of the conductive line, on sidewalls of the gap, and on the bottom of the gap are all different. Thus voids are easily generated in the silicon oxide layer. Voids in the silicon oxide layer seriously affect the device quality. While subsequently performing a chemical-mechanical polishing (CMP) step to planarize the silicon oxide layer, the voids are exposed so that slurry easily flows into these voids. Consequently, it is difficult to clean the slurry in the voids, which leads to contamination of the dielectrics. Device yield is thus decreased.
In order to solve aforementioned problems, a conventional method provides a nitrogen plasma treatment. However, the nitrogen plasma treatment needs one additional photomask and photoresist step so as to increase capital expenditure.
SUMMARY OF THE INVENTION
The invention provides an improved method of forming an inter-metal dielectric layer on a semiconductor substrate. A plurality of conductive lines is formed on the substrate wherein a gap is simultaneously formed between every two conductive lines to expose a part of the substrate. A conformal pad oxide layer is formed on the plurality of conductive lines and the exposed substrate. A spin-coating material layer is formed over the pad oxide layer. The spin-coating material layer is partially etched back to expose a portion of the pad oxide layer on top of the plurality of conductive lines wherein the remaining spin-coating material layer covers a part of the pad oxide layer at the bottoms and on sidewalls of the gaps. A plasma treatment is performed on the exposed pad oxide layer. The remaining spin-coating material layer is removed until the pad oxide layer is exposed. A first dielectric layer is formed over the pad oxide layer.
One advantage of the invention is that the nitrogen plasma treatment is just selectively performed in a region where overhang easily occurs at top corners of the conductive lines.
Moreover, another advantage of the invention is that the subsequent plasma can be performed in a self-aligned process. An additional photomask is not needed so as to save capital expenditure.
The invention can prevent overhang occurring on top corners of the conductive lines. Voids generated in a subsequently formed dielectric layer are avoided, and a dielectric layer with no voids can be formed. Thus, a gap filling ability of the dielectric layer is efficiently improved.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.


REFERENCES:
patent: 4940505 (1990-07-01), Schachameyer et al.
patent: 5494854 (1996-02-01), Jain
patent: 6008120 (1999-12-01), Lee
patent: 6030881 (2000-02-01), Papsouliotis et al.
patent: 6037018 (2000-03-01), Jang et al.

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