Method of fabrication of anti-fuse integrated with dual damascen

Details Method of fabrication of anti-fuse integrated with dual damascen Method of fabrication of anti-fuse integrated with dual damascen

1999-11-15

2000-09-26

Bowers, Charles

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

To form ohmic contact to semiconductive material

438132, 438215, 438281, 438601, 438622, 438624, 438637, 438675, 257529, 257530, H07L 2900

Patent

active

061241946

ABSTRACT:
A method of fabricating an anti-fuse module and dual damascene interconnect structure comprises the following steps. A semiconductor structure having at least two exposed metal lines covered by a first dielectric layer is provided. A first metal line is within an anti-fuse area and a second metal line is within an interconnect area. A first metal via is formed within the first dielectric layer within the anti-fuse area with the first metal via contacting the first metal line. A SiN layer is deposited over the first dielectric layer and the first metal via. The SiN layer is patterned to form at least two openings. A first opening exposes the first metal via, and a second opening exposes a portion of the first dielectric layer above the second metal line. A fusing element layer is deposited and patterned over the patterned SiN layered structure to form a fusing element over the first metal via. Simultaneously, an anti-fuse metal line is formed over the fusing element to form an anti-fuse module within the anti-fuse area, and a dual damascene interconnect is formed over, and contacting with, the second metal line and within the interconnect area.

REFERENCES:
patent: 5602053 (1997-02-01), Zheng et al.
patent: 5705849 (1998-01-01), Zheng et al.
patent: 5741626 (1998-04-01), Jain et al.
patent: 5877075 (1999-03-01), Dai et al.

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