Method of fabrication of a no-field MOS transistor

Details Method of fabrication of a no-field MOS transistor Method of fabrication of a no-field MOS transistor

2000-04-05

2002-02-26

Smith, Matthew (Department: 2825)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S305000, C438S286000, C438S298000, C438S450000

Reexamination Certificate

active

06350637

ABSTRACT:

TECHNICAL FIELD
The present invention relates to the field of integrated circuits, such as memory device chips. More specifically, the invention relates to MOS transistors capable of sustaining relatively high voltages.
BACKGROUND OF THE INVENTION
The improvements in integrated circuit manufacturing technology allow for a fast scaling down of the minimum achievable dimensions. This reflects on the operating voltages, which more or less decrease with the decrease of the minimum achievable dimension.
However, in some integrated circuits, such as non-volatile memory chips, the operating voltages necessary to perform particular operations, such as memory writing, do not decrease as fast as the minimum achievable dimension. In such integrated circuits, there is therefore the necessity of providing particular transistors, referred to as “high-voltage” transistors, that are capable of handling the relatively high voltages required for performing such particular operations. These high-voltage transistors are specifically designed to have a gate oxide suitably thicker than the gate oxide of the “low voltage” transistors of the remaining circuitry and dedicated channel profiles.
Other measures may be taken for realizing high-voltage transistors with the desired performance. For example, the doping levels of the source/drain regions are kept relatively low, in particular at the boundary between the source/drain regions and the field oxide, so that the breakdown voltage of the source/drain-to-substrate junctions is sufficiently higher than the memory writing voltage.
High-voltage transistors of the above type are also called “no field” transistors.
The provision of no field transistors requires modifications to the source/drain mask layout.
Specific additional problems arise when the manufacturing process provides for using the same dopant implantation forming the source/drain regions that are used for doping the polysilicon transistor gate, as in the case of processes for the integration of fast logic circuitry with non-volatile memories.
FIGS. 1 and 2
are top-plan views showing two of the most common techniques for obtaining no-field transistors.
In
FIG. 1
, reference numeral I denotes a portion of an integrated circuit wherein a no-field transistor is to be formed. Reference numeral
2
denotes the boundary of an active area portion of the circuit inside which the no-field transistor is formed; in other words, outside the boundary
2
a thick field oxide layer
3
is provided. A polysilicon strip
4
crosses the active area portion. The polysilicon strip
4
forming a gate electrode of the no-field transistor is separated from an underlying silicon substrate by means of a gate oxide layer. The polysilicon strip
4
, and the underlying gate oxide, divides the active area portion in two regions
5
, wherein the source/drain regions of the no-field transistor are formed. The region of the active area under the polysilicon gate forms a channel region of the no-field transistor.
The source/drain regions are normally relatively heavily doped N or P, formed by means of a relatively high dose dopant implant. In order to prevent the relatively high dose implant to extend up to the boundary
2
of the active area portion, an implant mask
6
is used which protects a region of the active area portion near the boundary
2
with the thick field oxide layer
3
.
The requirements for designing the implant mask
6
are the definition of the rules of overlapping of the protected zone towards the field oxide layer
3
and towards the gate
4
. In particular, the overlapping of the protected zone towards the gate
4
is critical when the polysilicon forming the gate is doped by the same implant used to form the source/drain regions. The region of overlapping of the implant mask
6
with the gate
4
must be negligible compared to the length L of the transistor, otherwise locally a transistor will form with features different from the expected ones. This inevitably leads to an increase in the transistor's length L, thus to a loss of performance and area. For these reasons, this technique is almost made impractical by the current layout rules.
The other commonly-used technique, depicted in
FIG. 2
where identical reference numerals are used to denote similar elements, provides for covering the boundary
2
of the active area portion with the polysilicon layer which forms the gate
4
of the transistor. Since the definition of the polysilicon layer precedes the dopant implantation for the formation of the source/drain regions, the technique of
FIG. 2
achieves the same result as that of
FIG. 1
, i.e., keeping the source/drain regions spaced apart from the boundary
2
of the active area.
This technique is not affected by the problems of the previous technique described above with respect to FIG.
1
. However, it is known that the corners of the active area, that is the corners of the field oxide layer
3
, are highly stressed and more probably subject to defects, so that the intersection of a polysilicon layer with the corners of the active area is to be avoided.
SUMMARY OF THE INVENTION
In view of the state of the art previously described, the disclosed embodiments of the present invention provide a method of fabrication of a no-field transistor that is not affected by the above-mentioned disadvantages.
According to the embodiments of the present invention, a method of fabrication of a no-field transistor is disclosed, providing for defining an active area for the transistor surrounded by a thick field oxide layer, insulatively placing a polysilicon gate electrode across the active area to define source/drain regions of the no-field transistor, providing an implant protection mask over a boundary between at least one of the source/drain regions and the field oxide layer, selectively implanting in said source/drain regions a relatively heavy dose of dopants to form relatively heavily doped source/drain regions and to simultaneously dope the polysilicon gate electrode. The polysilicon gate electrode is formed with lateral wings extending towards said at least one source/drain region, and in that said implant protection mask extends over said lateral wings but not over the polysilicon gate.
An advantage of the present invention resides in that it does not involve additional costs for the manufacturing of the no-field transistors.


REFERENCES:
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patent: 5556798 (1996-09-01), Hong
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patent: 62 229880 (1987-10-01), None
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patent: 04 254381 (1992-09-01), None
Oishi, T. et al., “Noticeable Enhancement of Edge Effect in Short Channel Characteristics of Trench-Isolated MOSFETs,”International Conference on Salid State Devices and Materials, JA, Japan Society of Applied Physics, Sep. 1998, pp. 86-87.

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