Method of fabrication of a field effect transistor with...

Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having schottky gate

Reexamination Certificate

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Details

C257S194000, C257S195000, C257SE29246, C257SE29247, C257SE29248, C257SE29249, C438S172000

Reexamination Certificate

active

07361536

ABSTRACT:
A semiconductor structure a structure with an enhancement mode transistor device disposed in a first region and depletion mode transistor device disposed in a laterally displaced second region. The structure has a channel layer for the depletion mode and enhancement mode transistor devices. An enhancement mode transistor device InGaP etch stop/Schottky contact layer is disposed over the channel layer; a first layer different from InGaP disposed on the InGaP layer; a depletion mode transistor device etch stop layer is disposed on the first layer; and a second layer disposed on the depletion mode transistor device etch stop layer. The depletion mode transistor device has a gate recess passing through the second layer and the depletion mode transistor device etch stop layer and terminating in the first layer. The enhancement mode transistor device has a gate recess passing through the second layer, the depletion mode transistor device etch stop layer, the first layer, and terminating in the InGaP layer.

REFERENCES:
patent: 5686741 (1997-11-01), Ohori et al.
patent: 6274893 (2001-08-01), Igarashi et al.
patent: 6670652 (2003-12-01), Song
patent: 6703638 (2004-03-01), Danzilio
patent: 2002/0177261 (2002-11-01), Song
patent: 2003/0168672 (2003-09-01), Takazawa et al.
patent: 2005/0110054 (2005-05-01), Wohlmuth
patent: 1 261 035 (2002-11-01), None
patent: 1 261 035 (2002-11-01), None
PCT/US2005/017710 International Search Report dated Dec. 12, 2005.

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