Method of fabricating wedge isolation transistors

Details Method of fabricating wedge isolation transistors Method of fabricating wedge isolation transistors

1999-10-01

2001-07-10

Bowers, Charles (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S199000, C438S223000, C438S229000, C438S231000, C438S289000, C438S305000

Reexamination Certificate

active

06258677

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates generally to methods of forming a transistor device with isolation regions, and specifically to forming wedge field effect transistor (FET) devices with raised source/drains separated by raised isolation regions.
BACKGROUND OF THE INVENTION
As transistor manufacturing delves into the sub micron and deep submicron range (less than 0.25 microns), the short channel length of the transistors so formed causes an effect named, appropriately enough, the short channel effect. Raised source/drain junctions can provide shallow junctions with low series resistance and that reduce the short channel effect. Raised isolation regions increase the electrical isolation between adjacent transistors and, for example, reduces undesired leakage current.
U.S. Pat. No. 5,915,183 to Gambino et al. describes a process for forming raised source/drain junctions using chemical-mechanical polishing (CMP) combined with a recess etch of blanket polysilicon. The raised source/drains are defined by salicide gate conductors and raised shallow isolation trench regions (STI).
U.S. Pat. No. 5,682,055 to Huang et al. describes a method of forming an improved planar structure of a semiconductor integrated circuit, and an integrated circuit formed therefrom.
U.S. Pat. No. 5,827,768 to Lin et al. describes a method of manufacturing a MOS (metal-oxide-semiconductor) transistor applied in the deep micron process. A polysilicon layer is mainly used to form a raised source/drain structure and self-alignment is achieved by means of a planarization process.
SUMMARY OF THE INVENTION
Accordingly, it is an object of the present invention to provide a method of forming transistors separated by wedge shaped raised isolation regions that increases electrical isolation between the transistors.
Another object of the present invention is to provide a method of forming transistors having raised source/drains separated by wedge shaped raised isolation regions that increases electrical isolation between the transistors.
A further object of the present invention is to provide a method of forming wedge shaped or re-entrant shallow trench isolation (STI) regions.
Yet a further object of the present invention is to provide a method of forming shallow trench isolation (STI) regions without the use of high density plasma (HDP) oxide fill and chemical-mechanical polishing (CMP) processes.
Other objects will appear hereinafter.
It has now been discovered that the above and other objects of the present invention may be accomplished in the following manner. Specifically, a silicon semiconductor structure having spaced, raised dielectric isolation regions defining an active region there between is provided. Epitaxial silicon is grown over the active area to form an SEG region. A dummy gate is formed over the SEG region. Raised epitaxial silicon layers are grown over the SEG region adjacent the dummy gate. The dummy gate is removed, exposing the interior side walls of the raised epitaxial silicon layers. Sidewall spacers are formed on the exposed sidewalls of the raised epitaxial silicon layers. A gate oxide layer is grown over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. A layer of polysilicon is deposited over the structure and is planarized to form a gate conductor over the SEG region and between the sidewall spacers of the raised epitaxial silicon layers. The sidewall spacers are removed.


REFERENCES:
patent: 5682055 (1997-10-01), Huang et al.
patent: 5773348 (1998-06-01), Wu
patent: 5798278 (1998-08-01), Chan et al.
patent: 5827768 (1998-10-01), Lin et al.
patent: 5915183 (1999-06-01), Gambino et al.
patent: 6110787 (2000-08-01), Chan et al.

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