Method of fabricating virtual ground SSI flash EPROM cell and ar

Details Method of fabricating virtual ground SSI flash EPROM cell and ar Method of fabricating virtual ground SSI flash EPROM cell and ar

1998-10-19

2000-05-09

Nelms, David

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438266, H01L 21336

Patent

active

060603569

ABSTRACT:
A compact, low current flash EPROM cell that is scaleable to dee-submicron levels for future generations of flash memory arrays is disclosed. This flash memory cell can be fabricated using a twelve masks, triple-poly, salicided process. Source-side injection for programming and poly-to-poly erasing demand very little current and power and such demand can easily be met by charge pump techniques. A select gate in series with the cell channel guarantees enhancement threshold and its sell-alignment and constant channel length will give uniform electrical characteristics in every respect. A virtual ground array fabricated using a self-aligned salicidation process provides a compact cell with high access speed. The cell area is approximately 3F.times.2F where F is a given minimum dimension.

REFERENCES:
patent: 5143860 (1992-09-01), Michell et al.
patent: 5242848 (1993-09-01), Yeh

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