Method of fabricating vertical FET with sidewall gate electrode

Details Method of fabricating vertical FET with sidewall gate electrode Method of fabricating vertical FET with sidewall gate electrode

1998-07-20

2000-12-05

Trinh, Michael

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438270, 438576, 438571, 438167, H01L 21336

Patent

active

06156611&

ABSTRACT:
A vertical FET is fabricated by etching through a contact layer into a drift layer on a compound semiconductor substrate to form a plurality of mesas, each mesa having an upper surface and each adjacent pair of mesas defining therebetween a trench with sidewalls and a bottom. A conductive layer is conformally deposited over the plurality of mesas and the trenches and anisotropically etched to form contacts on the sidewalls of the trenches and depositing source contacts on the upper surfaces of the mesas and a drain contact on a reverse side of the substrate.

REFERENCES:
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patent: 4295924 (1981-10-01), Garnache et al.
patent: 4568958 (1986-02-01), Baliga
patent: 4847214 (1989-07-01), Robb et al.
patent: 5447874 (1995-09-01), Grivna et al.
patent: 5705830 (1998-01-01), Siergiej et al.
patent: 5949124 (1999-09-01), Hadizad et al.

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