Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-02-22
2003-09-23
Elms, Richard (Department: 2824)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S218000, C438S294000, C438S296000
Reexamination Certificate
active
06624016
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates generally to semiconductor integrated-circuit manufacturing and more particularly to the formation of trench isolation for active devices on a semiconductor substrate.
2. Description of Related Art
The technique shallow-trench-isolation (STI) has become a major isolation technique for deep-submicrometer semiconductor devices in very high density integrated circuits. The major advantages of the STI technique over the conventional LOCOS technique are a smaller isolation area, a smaller thermal budget and a better planarized surface for fine-line lithography.
However, there are still several problems which appear in existing shallow-trench-isolation techniques. These problems can be found from U.S. Pat. No. 5,966,615 by Fazan et al., as shown in FIG.
1
. The oxide spacers
5
are formed on sidewalls of the planarized filling isolation-oxide layer
4
and are located in active regions having a pad-oxide layer
2
over the semiconductor substrate
1
, as shown in
FIG. 1A
, and
FIG. 1A
is then etched to remove the pad oxide layer
2
and to simultaneously etch the oxide spacers
5
. The small rounded caps or domes
4
A are remained over the trench corners for eliminating the leakage current due to the sharp corners, as shown in FIG.
1
B. Apparently, the caps or domes
4
A formed in
FIG. 1B
are quite similar to the bird's beaks of the conventional LOCOS isolation technique and the active area is sacrificed by the regions covered with the oxide spacers
5
. Moreover, the oxide spacers
5
are formed over sidewalls of planarized filling isolation-oxides
4
and both materials are oxides, a height and a width of the oxide spacers
5
become difficulty to be controlled using anisotropic dry etching, resulting in variations of the shape of the formed caps or domes
4
A. In addition, no field encroachments are performed for the semiconductor surface of an oxidized trench and a semiconductor surface under the formed caps or domes in order to reduce surface leakage currents.
Basically, a thermal oxidation of a trenched monocrystalline-silicon surface is needed in order to eliminate the trench etching-induced defects and, therefore, the bird's beak formation due to the thermal oxidation of existing trench isolation structures is inevitable. Although the trench corners are slightly rounded up through the thermal oxidation of the trenched surface, the corner tips must be properly capped to eliminate the field emission due to the trench corners without sacrificing the active area and the planarization of topography. Moreover, a proper field-encroachment implant is needed in order to eliminate the double-hump current-voltage characteristics of devices formed in the active regions due to the surface inversion layer being formed near the edges of the sharp corners and an excess leakage current due to the trench surface.
It is therefore an objective of the present invention to substantially eliminate these described problems together by creating buffer spacers in the trench-isolation regions. As a consequence, the thermal oxidation of the trench surface and a field-encroachment implant can be performed for the trench-isolation structure of the present invention without sacrificing the active area, and high-reliability and high-efficiency isolation structure for devices can be obtained.
SUMMARY OF THE INVENTION
The present invention uses two multilayer masking structures being formed separately on a monocrystalline-semiconductor substrate for forming two trench isolation structures. The first multilayer masking structure consists of a masking dielectric layer on a pad oxide layer; the second multilayer masking structure consists of a masking dielectric layer on a first conductive layer over a thin gate oxide layer. The multilayer masking structure is patterned and then etched anisotropically in a self-aligned manner to remove the multilayer masking structure for forming the isolation regions. The extended buffer spacers are formed on sidewalls of remained multilayer masking structure and the exposed monocrystalline-silicon substrates are then etched to form shallow trenches. A thermal oxidation of the etched trench surface is performed to form a thin thermal-oxide layer and the oxidized trench surface is implanted by a rotated large-angle-tilt implantation method to form field-encroachment implant regions. A trench-filling dielectric layer is then deposited to fill over an etched multilayer masking structure and the planarization using the chemical-mechanical-polishing (CMP) technique is performed to remove the excess trench-filling dielectric layer over the masking dielectric layer. The planarized trench filling dielectric layer is anisotropically etched back to a depth slightly higher than a height of the pad-oxide layer for the first multilayer masking structure and to a depth approximately equal to a thickness of the masking dielectric layer for the second multilayer masking structure, and then both the masking dielectric layers are removed. The pad-oxide layer is removed anisotropically for the first multilayer masking structure and the capping-dielectric layers due to the extended buffer spacers are remained on the corners of the trenches, then a thin gate-oxide layer is formed thermally and a conductive layer acted as a gate material is deposited; however, for the second multilayer masking structure the second conductive layer is deposited. Both planarized structures are ready to define the gate lengths and further to form source and drain diffusion regions of devices using the well-known techniques. Apparently, the extended buffer spacers are formed in the isolation regions and the active area is not sacrificed. Moreover, the thermal-oxide layer grown on the trench surface and the field-encroachment implant of the trench surface are all located under the extended buffer spacers in the isolation regions without sacrificing the active area and the surface planarization. Therefore, high-reliability and high-efficiency trench isolation for scaled devices can be easily obtained by the present invention.
REFERENCES:
patent: 6080628 (2000-06-01), Cherng
Elms Richard
Moga Thomas T.
Owens Beth E.
Silicon-Based Technology Corporation
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