Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1999-09-14
2000-07-25
Monin, Jr., Donald L.
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438585, 438303, H01L 21336, H01L 218234
Patent
active
060935901
ABSTRACT:
A method of fabricating a transistor. A first dielectric layer with a high dielectric constant is formed on a substrate. An oxide layer is formed on the first dielectric layer. A silicon nitride layer is formed on the oxide layer. The silicon nitride layer, the oxide layer, and the first dielectric layer are patterned to form a dummy gate structure. A spacer is formed on a sidewall of the dummy gate structure. The spacer and the dummy gate structure together form a dummy gate. An ion implantation step with the dummy gate serving as a mask and a thermal annealing step are performed to form a source region and a drain region on opposite sides of the dummy gate in the substrate. A second dielectric layer is formed next to the spacer. A top surface of the second dielectric layer is approximately level with a top surface of the dummy gate structure. The silicon nitride layer is removed. A nitridation process is performed to convert the oxide layer into a nitride layer. A metal barrier layer is formed over the substrate to cover the second dielectric layer, the spacer, and the nitride layer. A metal layer is formed on the metal barrier layer. A planarization process is performed to remove a portion of the metal layer and the metal barrier layer to form a metal gate. A top surface of the metal gate is level with a top surface of the second dielectric layer.
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patent: 5960270 (1999-09-01), Misra et al.
patent: 5966597 (1999-10-01), Wright
patent: 5994193 (1999-11-01), Gardner et al.
Huang Jiawei
Monin, Jr. Donald L.
Pham Hoai
Worldwide Semiconductor Manufacturing Corp.
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