Method of fabricating strained silicon transistor

Details Method of fabricating strained silicon transistor Method of fabricating strained silicon transistor

2011-05-31

2011-05-31

Nguyen, Thanh (Department: 2893)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S197000, C438S201000, C438S275000, C257SE21616

Reexamination Certificate

active

07951662

ABSTRACT:
A method of fabricating a strained silicon transistor is provided. Amorphous silicon is formed below the transistor region before the transistor is formed. By using the tensile/compressive strainer, amorphous silicon is recrystallized to form a strained silicon layer. In addition, the dopants in the well can be driven in and activated by using the same annealing process with the amorphous silicon recrystallization.

REFERENCES:
patent: 2005/0285187 (2005-12-01), Bryant et al.
patent: 2007/0190741 (2007-08-01), Lindsay
patent: 2008/0081382 (2008-04-01), Yang et al.
A. Wei et al., “Multiple Stress Memorization In Advanced SOI CMOS Technologies”, 2007, pp. 216-217, 2007 Symposium on VLSI Technology Digest of Technical Papers.

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