Method of fabricating storage node electrode, for DRAM devices,

Details Method of fabricating storage node electrode, for DRAM devices, Method of fabricating storage node electrode, for DRAM devices,

1996-11-25

1998-06-16

Nguyen, Tuan H.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438396, 148DIG14, H01L 218242

Patent

active

057669937

ABSTRACT:
A method for creating an STC structure, used for high density, DRAM designs, has been developed. The process consists of creating a storage node electrode, for the STC structure, consisting of an upper polysilicon shape, comprised of polysilicon columns, with a narrow space between polysilicon columns, and an underlying lower polysilicon shape, residing in a contact hole, and making contact to underlying transistor regions. A key feature of this invention is to create a narrow trench, in a polysilicon layer, via anisotropic etching of the polysilicon layer, using a very narrow opening in a photoresist layer, as a mask. The very narrow opening is obtained by creation of non-volatile polymer spacers, on the sides of a minimum opening in the photoresist layer. The narrow trench defines the narrow spaces between polysilicon columns, while subsequent photolithographic, and dry etching patterning, define the storage node electrode, with protruding polysilicon columns. This storage node electrode configuration results in increased surface area, via use of polysilicon columns, as well as density improvements, resulting from the use of narrow spaces between polysilicon columns.

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