Method of fabricating staggered thin film transistor with an imp

Details Method of fabricating staggered thin film transistor with an imp Method of fabricating staggered thin film transistor with an imp

1997-12-05

2000-07-11

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

On insulating substrate or layer

148DIG53, 438161, H01L 2100

Patent

active

060872055

ABSTRACT:
A method of forming multi-layer structure of source/drain electrodes and an amorphous silicon layer in a forward staggered thin film transistor. Source/drain electrodes are selectively provided on an insulator. Each of the source/drain electrodes comprises an undoped transparent conductive film on the insulator and an impurity doped transparent conductive film on the insulator and an impurity doped transparent conductive film extending over the undoped transparent conductive film. An amorphous silicon active layer extends over the source/drain electrodes and a top surface of the insulator so that the amorphous silicon active layer over the source/drain electrodes has an impurity diffused interface in contact with the impurity doped transparent conductive film to form ohmic contacts between the impurity doped transparent conductive film and the amorphous silicon active layer. The amorphous silicon active layer in contact wit the top surface of the insulator between the source/drain electrodes is free of impurities.

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