Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Patent
1998-03-17
1999-11-16
Utech, Benjamin
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
438256, 438397, 438399, 117 7, H01L 27108
Patent
active
059857153
ABSTRACT:
A method of fabricating a stacked type capacitor. A semiconductor substrate having a transistor, a field oxide layer, and a conductive layer formed on top of the field oxide layer is provided. The transistor comprises a gate and a source/drain region. A first dielectric layer is formed over the substrate. An oxide layer is formed over the first dielectric layer. A second dielectric layer is formed on the oxide layer. An etching step is performed to the second dielectric layer to form an opening therein. A first poly-silicon layer is formed on the second dielectric layer and the opening. The first poly-silicon layer is etched back to remove a part of the first poly-silicon layer. A first spacer is formed on a wall of the opening. The oxide layer is etched for a first height by using the first spacer and the second dielectric layer as a first mask. A second poly-silicon layer is formed on the second dielectric layer and the opening. An etching back is performed to the second poly-silicon layer to remove a part of the second poly-silicon layer. A second spacer is formed on a wall of the first height in the opening. The oxide layer is etched for a second height by using the first spacer, the second spacer, and the second dielectric layer as a second mask, and a third spacer is formed. The first dielectric layer is formed to expose the source/drain region. Selective epitaxy growth is performed to form an epitaxy layer on the first spacer, the second spacer, and the third spacer. The second dielectric layer and the oxide layer are removed to form a bottom electrode. A third dielectric layer is formed on the bottom electrode. A top electrode is formed on the third dielectric layer.
REFERENCES:
patent: 4811076 (1989-03-01), Tigelaar et al.
patent: 5405801 (1995-04-01), Han et al.
patent: 5478768 (1995-12-01), Iwasa
patent: 5811332 (1998-09-01), Chao
patent: 5909045 (1999-06-01), Chao
Anderson Matthew
Utech Benjamin
Winbond Electronics Corp.
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