Method of fabricating shallow trench isolation

Details Method of fabricating shallow trench isolation Method of fabricating shallow trench isolation

1998-11-30

2001-06-12

Booth, Richard (Department: 2812)

Semiconductor device manufacturing: process

Formation of electrically isolated lateral semiconductive...

Total dielectric isolation

C438S423000, C438S433000

Reexamination Certificate

active

06245635

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor fabricating method. More particularly, the present invention relates to a method of fabricating an isolation region.
2. Description of the Related Art
An isolation region is formed in an integrated circuit for the purpose of separating neighboring device regions of a substrate and preventing the carriers from penetrating through the substrate to neighboring devices. In a dynamic random access memory (DRAM) device, for example, the field effect transistors (FETs) are isolated from each other by isolation regions in order to prevent current leakage among the FETs. Conventionally, local oxidation of silicon (LOCOS) technique is widely utilized in the semiconductor industry to provide isolation regions among the various devices in the substrate. Since the LOCOS technique has been used for quite a period of time, it is one of the most reliable and low-cost method for fabricating the device isolation regions. However, there are still some difficulties in the LOCOS process. These include internal stress generation and bird's beak encroachment. For a highly integrated device, the problem of bird's beak encroachment by the isolation regions is especially difficult to avoid and thus the isolation regions cannot effectively isolate devices.
Shallow trench isolation (STI) technique is the other conventional method of forming isolation regions. A shallow trench isolation is formed by first anisotropically etching to form a trench in the substrate, and then depositing oxide in the trench to form an isolation region. Since shallow trench isolation is scaleable and has no bird's beak encroachment problem as found in the conventional LOCOS technique, it has become widely used for forming sub-micron CMOS circuits.
FIGS. 1A through 1B
are schematic, cross-sectional views showing a conventional method of fabricating a shallow trench isolation.
In
FIG. 1A
, a patterned mask layer
104
is formed on a substrate
100
. The patterned mask layer
102
is used as an etching mask when an etching step is performed. Trenches
107
and
108
are formed in the substrate
100
by etching. A silicon oxide layer
116
is formed over the substrate
100
to cover the patterned mask layer
104
. The trenches
107
and
108
are filled by the silicon oxide layer
116
.
In
FIG. 1B
, a planarization process is performed, first by chemical-mechanical polishing, and then by etching. The patterned mask layer
104
is used as a polishing stop layer. A portion of the silicon oxide layer
116
is removed by chemical-mechanical polishing (CMP) until the patterned mask layer
114
is exposed. The patterned mask layer
104
is removed by etching while retaining portions of silicon layer
116
in the trenches
107
and
108
, which completes construction of isolation regions
117
and
118
. The isolation regions
117
and
118
are used to isolate active regions of the substrate
100
.
In the steps described above, the patterned mask layer
104
is harder than the silicon oxide layer
116
so that the patterned mask layer
104
can be used as the polishing stop layer while a portion of the silicon oxide layer
116
is removed. Hence, surface planarization is achieved.
However, variations in pattern density can lead to variation density of the patterned mask layer
104
. Thus, after chemical-mechanical polishing, both the wide isolation regions
117
and the narrow isolation regions
118
are formed. The variation density of the patterned mask layer
104
causes local nonuniformity in the CMP process. In other words, the mask layer
104
is used as the polishing stop layer when chemical-mechanical polishing is performed. Additionally, the load of wide isolation regions
117
and load of narrow isolation regions
118
are different. The high-density active regions isolated by narrow isolation regions
118
have correspondingly more polishing stop material provided by the mask layer
104
. The CMP process tends to equalize the surface of the mask
104
and the uppermost surface of the narrow isolation regions
118
. After the planarization process, each surface
148
of the narrow isolation regions
118
is roughly level with the substrate surface
142
. In contrast with the narrow isolation regions
118
, the wide isolation regions
117
have correspondingly less polishing stop material. Therefore, the isolation regions
117
are easily dished by polishing, which is called a dishing effect. Furthermore, the surface
140
can be recessed below the surface
142
of the substrate
100
, which further leads to the exposed corner regions
144
of the trenches
107
. The gate oxide layer (not shown) and the gate conductive layer will cover the corner regions
144
in the following step of forming a MOS transistor (not shown). The presence of the corner regions
144
in the MOS transistor can cause sub-threshold leakage current in a channel region of the MOS transistor during the periods when the MOS transistor is switched off.
In addition, the CMP process is accomplished by abrading the surface of the silicon oxide layer
116
with a slurry. Since particles of the slurry are harder than silicon oxide, the surface of the silicon oxide layer
116
is easily scratched by the particles, which scratching results in the formation of microscratches. The microscratches in the surface of the silicon oxide layer
116
easily become deep scratches
146
after the subsequent steps, such as a cleaning step and an etching step, for example. The gate conductive layer easily remains in the scratches. In this manner, bridges between MOS transistors in neighboring active regions beside isolation regions occur.
To overcome the local nonuniformity in the CMP process cited above, a method is provided as described in Suresh Venkatesan et al., U.S. Pat. No. 5,459,096, “Process for Fabricating a Semiconductor Device Using Dual Planarization Layers”. Reference is made to
FIGS. 2A through 2C
, which explains the fabricating process proposed by Suresh Venkatesan et al.
In
FIG. 2A
, a substrate
200
having recessed regions
210
and elevated regions
212
is provided. A pad oxide layer
202
and a planarization layer
204
are formed in sequence over the elevated regions
212
of the substrate
200
. A liner layer
214
is formed on the recessed regions
210
. A fill material is
216
deposited over the substrate
200
to fill the recessed regions
210
and cover the planarization layer
204
.
In
FIG. 2B
, portions of the oxide layer
216
are removed to expose portions of the planarization layer
204
above the elevated regions
212
. The fill material
216
is removed to leave dielectric portions
216
a
. A silicon nitride layer
220
is formed over the substrate
200
to cover the dielectric portions
216
a
and the planarization layer
204
. Because of the topographic contrast in the substrate
200
creased by recessed regions
210
and elevated regions
212
, the dielectric portions
216
a
has protruding regions at the edge of dielectric portions
216
a.
In
FIG. 2C
, a planarization process is performed by chemical-mechanical polishing and wet etching. The dielectric portions
216
b
remaining from the dielectric portions
216
a
is level with the surface of the elevated regions
212
.
In the method described above, the fill material
216
above the elevated regions
212
is removed at first to expose the planarization layer
204
. Then, the planarization layer
220
is formed over the substrate
200
. The planarization layer
220
above the recessed regions
210
and the planarization layer
204
are used as polishing stop layers to protect the dielectric portions
216
a
in the recessed regions
210
in the following CMP process. In this manner, local nonuniformity in a CMP process arising from the variations in the pattern density can be reduced.
SUMMARY OF THE INVENTION
It is an object of the invention to provide a method to fabricate a shallow trench isolation. In the invention, formation of the polishing stop layer prevent

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