Method of fabricating semiconductor integrated circuit

Details Method of fabricating semiconductor integrated circuit Method of fabricating semiconductor integrated circuit

2006-11-14

2006-11-14

Wojciechowicz, Edward (Department: 2815)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S205000, C438S234000, C438S353000, C438S355000, C438S356000, C438S357000, C438S416000, C257S499000, C257S565000

Reexamination Certificate

active

07135364

ABSTRACT:
The lateral pnp transistor encompasses a p-type semiconductor substrate, an n-type first buried region disposed on the semiconductor substrate, an n-type uniform base region disposed on the first buried region, an n-type first plug region disposed in the uniform base region, a p-type first emitter region and a first collector region disposed in and at the top surface of the uniform base region, a graded base region disposed in the uniform base region and a first base contact region disposed in the first plug region. The graded base region encloses the bottom and the side of the first main electrode region. The doping profile in the graded base region intervening between the first emitter region and the first collector region is such that the impurity concentration is gradually decreases towards the second main electrode region from the first main electrode region.

REFERENCES:
patent: 4110126 (1978-08-01), Bergeron et al.
patent: 4149906 (1979-04-01), De La Moneda
patent: 4196440 (1980-04-01), Anantha et al.
patent: 4326212 (1982-04-01), Bergeron et al.
patent: 5326710 (1994-07-01), Joyce et al.
patent: 5665994 (1997-09-01), Palara
patent: 5708290 (1998-01-01), Cacciola et al.
patent: 6033947 (2000-03-01), Cacciola et al.
patent: 6225181 (2001-05-01), Gregory
patent: 6242793 (2001-06-01), Colombo et al.
patent: 0 435 541 (1991-07-01), None
patent: 0 545 488 (1993-06-01), None
patent: 55-22875 (1980-02-01), None
patent: 55022875 (1980-02-01), None
patent: 56-60049 (1981-05-01), None
patent: 56060049 (1981-05-01), None
patent: 5-74790 (1993-03-01), None
patent: 9-275154 (1997-10-01), None
patent: 2000-31160 (2000-01-01), None
Michael P. Masquelier and David N. Okada, Institute of Electrical and Electronics Engineers, “Integration of a 200V, 60MHz Lateral PNP Transistor with Emitter-Base Self-Aligned to Polysilicon, into a High Voltage BiCMOS Process”, Proceedings of the 3rdInternational Symposium on Power Semiconductor Devices and ICs, pp. 56-60, XP000216972, 1991 IEEE , Apr. 22-24, 1991, Baltimore, Maryland, USA.

Affiliated with

Also associated with

Rating

Method of fabricating semiconductor integrated circuit does not yet have a rating. At this time, there are no reviews or comments for this patent.

If you have personal experience with Method of fabricating semiconductor integrated circuit, we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor integrated circuit will most certainly appreciate the feedback.

Rate now

Comments { 0 }

Profile ID: LFUS-PAI-O-3695029