Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-01-12
2003-01-14
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S239000, C438S396000
Reexamination Certificate
active
06506644
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention generally relates to semiconductor devices and, more particularly, to a miniaturized semiconductor device and a fabrication process thereof in which leakage current is minimized.
2. Description of the Related Art
With the continuous progress of device miniaturization, the integration density of semiconductor integrated circuit devices, particularly the integration density of memory semiconductor integrated circuit devices, is increasing every year. These days, intensive investigations are being made on so-called sub-halfmicron devices having a minimum pattern width of 0.3 &mgr;m or less.
In a DRAM (dynamic random access memory) that stores information in a memory cell capacitor in the form of electric charges, the device miniaturization inevitably causes a decrease in the capacitance of the memory cell capacitor, and there is a tendency that the retention of information in the memory cell capacitor becomes unstable. Further, the read/write operation may become also unstable in such extremely miniaturized DRAMs. Similar problems also occur in so-called flash memory devices in which information is stored in a floating gate in the form of electric charges. Thus, various efforts are being made for stabilizing the operation of the miniaturized DRAMs and flash memories.
FIGS. 1A-1F
show a conventional fabrication process of a DRAM.
Referring to
FIG. 1A
, an active region is defined on an Si substrate
1
typically doped to the p-type, by providing a field oxide film
2
A and SiO
2
on the Si substrate
1
, and a thin thermal oxide film
2
B also of SiO
2
is formed on the active region thus defined on the Si substrate
1
by the field oxide film
2
A. Further, a word line WL of polysilicon is provided on the Si substrate
1
so as to extend over the substrate
1
thus covered by the field oxide film
2
A and further the thermal oxide film
2
B, wherein the word line WL extends over the thermal oxide film
2
B in the active region and the word line WL thus extending over the thermal oxide film
2
B forms a gate electrode of a memory cell transistor. Thereby, the thermal oxide film
2
B forms a gate insulation film of the memory cell transistor.
In the step of
FIG. 1A
, an ion implantation process of P
+
is conducted further into the Si substrate
1
while using the gate electrode
3
as a self-aligned mask, and there are formed diffusion regions
1
A and
1
B of the memory cell transistor in the Si substrate
1
at both lateral sides of the gate electrode
3
.
Next, in the step of
FIG. 1B
, an oxide film
4
of SiO
2
is deposited on the structure of
FIG. 1A
by a high temperature CVD process so as to cover the gate electrode
3
, and an anisotropic etching process acting generally perpendicularly to a principal surface of the substrate
1
is applied to the thermal oxide film
4
in the step of
FIG. 1C
by an RIE (reactive ion etching) process, to form side wall oxide films
4
A and
4
B covering both side walls of the gate electrode
3
. In the step of
FIG. 1C
, it is also possible, while not illustrated, to conduct an ion implantation process of P
+
while using the gate electrode
3
and further the side wall oxide films
4
A and
4
B as a self-aligned mask, to form a so-called LDD (lightly-doped drain) structure.
Next, in the step of
FIG. 1D
, an interlayer insulation film
5
of BPSG (borophosophosilicate glass) is deposited on the structure of
FIG. 1C
, followed by a formation of a contact hole SA in the interlayer insulation film
5
so as to expose the diffusion region
1
A. Further, an electrode
6
is provided as a part of a bit line such that the electrode
6
fills the contact hole
5
A and achieves an electrical contact to the exposed diffusion region
1
A.
Further, in the step of.
FIG. 1E
, another interlayer insulation film
7
of BPSG is deposited on the structure of
FIG. 1D
, followed by a formation of a contact hole
7
A penetrating through the interlayer insulation films
7
and
5
such that the contact hole
7
A exposes the foregoing diffusion region
1
B.
Finally, in the step of
FIG. 1F
, an accumulation electrode
8
A of polysilicon is formed so as to fill the contact hole
7
A in electrical contact with the diffusion region
1
B, and a dielectric film
8
B having a so-called ONO structure, in which a thin SiN film is vertically sandwiched by a pair of thin SiO
2
films, is provided so as to cover the accumulation electrode
8
A. Further, an opposing electrode
8
C of polysilicon is provided so as to cover the foregoing dielectric film
8
B. Thereby, the electrode
8
A, the dielectric film
8
B and the opposing electrode
8
C form together a memory cell capacitor
8
.
In the DRAM of the foregoing conventional structure, it has been discovered that there are cases in which a leakage current flows between the accumulation electrode
8
A and the gate electrode
3
when the DRAM is miniaturized particularly to the degree in which the minimum pattern width is 0.3 &mgr;m or less. As the accumulation electrode
8
A forms a part of the memory cell capacitor
8
that holds the information in the form of electric charges, the leakage current occurring in the electrode
8
A causes a serious problem in the operation of the DRAM, particularly the stability of data retention. an enlarged scale.
Referring to
FIG. 2A
, it can be seen that the gate electrode
3
carries an anti-reflection film
3
A that has been used for patterning the gate electrode
3
. Further, a CVD oxide film
5
B is provided between the side wall oxide film
4
A or
4
B and the interlayer insulation film
5
. In order to secure a sufficient distance between the gate electrode
3
and the electrode
8
A in the contact hole
5
A, the contact hole
5
A is formed to have a tapered structure in which the diameter reduces gradually from a top surface to a bottom surface of the contact hole
5
A.
In such sub-halfmicron DRAMs having a minimum pattern width of 0.3 &mgr;m or less, it is actually difficult to form the contact hole
5
A in the ideally aligned state as shown in
FIG. 2A
, and actual devices generally have a structure shown in
FIG. 2B
, in which it will be noted that the contact hole
5
A is offset from the ideal state of FIG.
2
A. In the structure of
FIG. 2B
, the accumulation electrode
8
A filling the contact hole
5
A approaches the gate electrode
3
, and it is believed that such a reduction in the distance between the gate electrode
3
and the electrode
8
A causes the leakage current to flow between the accumulation electrode
8
A and the gate electrode
3
, although the exact current path of the leakage current is not fully explored yet.
As will be explained later, the problem of leakage current appears particularly conspicuous when an etching is applied to the diffusion region
1
B by a buffered HF solution for removing a oxide film from the surface of the diffusion region
1
B.
SUMMARY OF THE INVENTION
Accordingly, it is a general object of the present invention to provide a novel and useful semiconductor device and a fabrication process thereof wherein the foregoing problems are eliminated.
Another and more specific object of the present invention is to provide a semiconductor device having a gate electrode in which leakage current to the gate electrode from an opposing electrode is successfully minimized, as well as a fabrication process thereof.
Another object of the present invention is to provide a semiconductor device., comprising:
a substrate;
a gate electrode provided on said substrate;
a side wall insulation film covering a side wall of said gate electrode;
a diffusion region formed in said substrate adjacent to said gate electrode;
an ohmic electrode formed on said diffusion region; and
a nitride film provided between said side wall insulation film and said wall of said gate electrode, such that said nitride film covers a part of a surface of said gate electrode facing said ohmic electrode.
Another object of the present invention is to provide a method of fabricating a semicondu
Armstrong Westerman & Hattori, LLP
Chaudhari Chandra
Chen Jack
Fujitsu Limited
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