Method of fabricating semiconductor devices with raised doped re

Details Method of fabricating semiconductor devices with raised doped re Method of fabricating semiconductor devices with raised doped re

1998-03-19

2000-09-05

Niebling, John F.

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438299, 438691, 438692, H01L 21336

Patent

active

061142093

ABSTRACT:
A method of manufacturing a semiconductor device with raised source/drain. This method eliminates the problem which is often experienced when the shallow junction technique is applied, in which over-etching of the source/drain region during the contact etching and the salicide process can lead to current leakages. The improved method includes the steps of forming a buffer conductive blocks on the source/drain regions which increase the thickness of source/drain regions. A related semiconductor structure made by the method has a plurality of bi-flange shape side wall spacers by which the semiconductor structure not only elevates the doped regions, it also provides an improved capability to suppress the electric bridges between the gate electrode and source/drain regions, respectively.

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Chiu et al "Nonoverlapping super self-aligned device structure for high-performance VLSI," IEEE Elect. Device Lett., vol. 11, No. 2, pp. 85, Feb. 1990.

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