Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2002-03-25
2004-08-03
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S566000, C438S730000
Reexamination Certificate
active
06770540
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, to a method of fabricating a semiconductor device having an L-shaped spacer.
2. Description of the Related Art
In general, spacers are formed at both sidewalls of a gate electrode to provide an implant mask for forming a source and drain region and to provide electrical isolation between the gate electrode and the source and drain electrodes during silicide processing. Here, a conventional method of fabricating a semiconductor device having an L-shaped spacer will be described with reference to U.S. Pat. No. 5,783,475 by Motorola, Inc., Shrinath Ramaswami, entitled “Method of Forming a Spacer”.
FIGS. 1 through 5
illustrate a conventional method of fabricating a semiconductor device having an L-shaped spacer.
Referring to
FIG. 1
, a gate dielectric layer
33
is formed on a semiconductor substrate
31
, for example, a silicon substrate. Subsequently, a gate electrode
32
is formed on the gate dielectric layer
33
. The gate dielectric layer
33
is formed of silicon oxide (SiO
2
) or silicon nitride (Si
3
N
4
), and the gate electrode
32
is formed of polysilicon. Subsequently, a first dielectric layer
48
is formed on the surface of the gate electrode
32
and on the semiconductor substrate
31
. The first dielectric layer
48
is formed of silicon oxide (SiO
2
). Next, a shallowly doped source region
34
and a shallowly doped drain region
35
are formed in the semiconductor substrate
31
on both sides of the gate electrode
32
by implanting impurities in the entire surface of the semiconductor substrate
31
, on which the gate electrode
32
and the first dielectric layer
48
are formed.
Referring to
FIG. 2
, a second dielectric layer
36
and a third dielectric layer
37
are formed on the first dielectric layer
48
to form spacers. The second dielectric layer
36
is formed of silicon nitride (Si
3
N
4
), and the third dielectric layer
37
is formed of silicon oxide (SiO
2
).
Referring to
FIG. 3
, the third dielectric layer
37
is anisotropically etched to form a first spacer
37
at both sidewalls of the gate electrode
32
. The shallowly doped source region
34
, the shallowly doped drain region
35
, and the second dielectric layer
36
formed on the gate electrode
32
are exposed at portions marked by reference numerals
38
,
40
, and
39
, respectively.
Referring to
FIG. 4
, the second dielectric layer
36
formed on the shallowly doped source region
34
, the shallowly doped drain region
35
, and the second dielectric layer
36
on the gate electrode
32
at portions marked by reference numerals
38
,
40
, and
39
, respectively, are etched to form a second spacer
36
at both sidewalls of the gate electrode
32
. Etching the second dielectric layer
36
is performed by a wet etch using phosphoric acid, and portions masked by the third dielectric layer
37
and the first dielectric layer
48
are not etched. Subsequently, impurities are implanted in the entire surface of the semiconductor substrate
31
by using the first spacer
37
and the second spacer
36
as a mask and then annealed to form a deeply doped source region
43
and a deeply doped drain region
44
. As a result, a source and drain extension is formed of the shallowly doped source region
34
and the shallowly doped drain region
35
adjacent to the deeply doped source region
43
and the deeply doped drain region
44
.
Referring to
FIG. 5
, the first spacer
37
, and the first dielectric layer
48
formed on the deeply doped source region
43
and the deeply doped drain region
44
and the gate electrode
32
are removed at portions marked by reference numerals
38
,
40
, and
39
. Etching the first dielectric layer
48
is performed by using hydrofluoric (HF) solution. In this case, surfaces of the gate electrode
32
and the deeply doped source region
43
and the deeply doped drain region
44
are exposed. Subsequently, salicide contacts
45
,
46
, and
47
are formed on the deeply doped source region
43
, the gate electrode
32
, and the deeply doped drain region
44
, respectively.
In the conventional method of fabricating a semiconductor device, impurities, which are necessarily shallowly doped during an annealing process for forming the deeply doped source region
43
and deeply doped drain region
44
, are spread over the shallowly doped source region
34
and the shallowly doped drain region
35
. In such a case, a short channel effect occurs in a highly integrated semiconductor device.
SUMMARY OF THE INVENTION
To solve the above problems, it is an objective of the present invention to provide a method of fabricating a semiconductor device having an L-shaped spacer which is capable of preventing a short channel effect.
Accordingly, to achieve the objective, there is provided a method of fabricating a semiconductor device. A gate dielectric layer and a gate electrode are formed on a semiconductor substrate, and a buffer dielectric layer, a first dielectric layer, and a second dielectric layer are sequentially formed on the surface of the gate electrode and on the semiconductor substrate. The second dielectric layer is etched to form a first disposable spacer on the first dielectric layer at both sidewalls of the gate electrode, and a deeply doped source and drain region is formed on the semiconductor substrate to be aligned to the first disposable spacer.
The first disposable spacer and the first dielectric layer are sequentially removed, and a shallowly doped source and drain region is formed on the semiconductor substrate at both sidewalls of the gate electrode adjacent to the deeply doped source and drain region. A third dielectric layer, a fourth dielectric layer, and a fifth dielectric layer are formed on the buffer dielectric layer, and the fifth dielectric layer is etched to form a second disposable spacer on the fourth dielectric layer at both sidewalls of the gate electrode. The fourth dielectric layer, the third dielectric layer, and the buffer dielectric layer are etched to form an L-shaped spacer at both sidewalls of the gate electrode, and a metal silicide is formed on top of the gate electrode and on the deeply doped source and drain region.
The second dielectric layer is formed of a layer having a high etching selectivity to the first dielectric layer. For example, the second dielectric layer is formed of silicon oxide (SiO
2
), and the first dielectric layer is formed of silicon nitride (Si
3
N
4
). The first dielectric layer is formed of a layer having a high etching selectivity to the buffer dielectric layer. For example, the first dielectric layer is formed of silicon nitride (Si
3
N
4
), and the buffer dielectric layer is formed of silicon oxide (SiO
2
).
The deeply doped source and drain region is formed by performing a step of implanting impurities by using the first disposable spacer as a mask and a step of annealing the implanted impurities. The step of annealing to form the deeply doped source and drain region is performed before the shallowly doped source and drain region is formed. The shallowly doped source and drain region is formed by performing a step of implanting impurities in the entire surface of the semiconductor substrate, on which the buffer dielectric layer is formed, and a step of annealing the implanted impurities. The step of annealing to form the shallowly doped source and drain region is performed before the metal silicide is formed. The step of annealing to form the shallowly doped source and drain region is performed at a low temperature of 500-800° C. or by a rapid thermal annealing method or a spike thermal annealing method at a temperature of 900-1300° C.
The fifth dielectric layer is formed of a layer having a high etching selectivity to the fourth dielectric layer. For example, the fifth dielectric layer is formed of silicon oxide (SiO
2
), and the fourth dielectric layer is formed of silicon nitride (Si
3
N
4
).
The distance from the sidewalls of the gate electro
Fourson George
Harness Dickey & Pierce PLC
Toledo Fernando L.
LandOfFree
Method of fabricating semiconductor device having L-shaped... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating semiconductor device having L-shaped..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating semiconductor device having L-shaped... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3297012