Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-12-17
2003-09-02
Cuneo, Kamand (Department: 2829)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S199000, C438S232000, C438S514000, C438S522000, C438S525000
Reexamination Certificate
active
06613635
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more particularly, it relates to a method of fabricating a semiconductor device having an element isolation trench.
2. Description of the Prior Art
In recent years, further reduction of a design rule is studied in order to improve the degree of integration and the speed of a semiconductor device. At present, prototypes of a 256-M DRAM (Dynamic Random Access Memory) and a CMOS (Complementary Metal Oxide Semiconductor) transistor having a gate length of 0.1 &mgr;m are opened to the public. Following such progress of refinement of the transistor, reduction of the device size according to a scaling law and following increase of the operating speed are expected.
In relation to miniaturization of the device, it is extremely important to improve an element isolation technique for isolating refined transistors from each other in addition to refinement of the transistor.
In general, the LOCOS (local oxidation of silicon) method is employed for element isolation. In the LOCOS method, however, the element isolation width cannot be sufficiently reduced due to lateral spreading (bird's beak) of a silicon oxide film for isolating elements from each other by oxidation isolation.
To this end, STI (shallow trench isolation) of forming a trench for element isolation between elements and embedding a silicon oxide film in the trench thereby isolating the elements from each other is proposed.
When STI is employed, the element isolation width is not limited by a bird's beak dissimilarly to the LOCOS method, whereby the device can be further refined.
When STI is employed, however, an upper corner portion of the trench is sharply shaped as compared with that in the LOCOS method. When a transistor is fabricated, therefore, an electric field from a gate electrode to a channel region concentrates on the upper corner portion of the trench, to disadvantageously reduce a threshold voltage in the upper corner portion of the trench. Further, a leakage current disadvantageously readily flows through the portion having the reduced threshold voltage.
A method of suppressing field concentration on the upper corner portion of the trench by rounding this upper corner portion is known as a method of avoiding the aforementioned problems caused in the STI. Also when reduction of the threshold voltage caused by field concentration is suppressed, however, the threshold voltage disadvantageously fluctuates due to diffusion of an impurity in the upper corner portion of the trench. In an nMOSFET, for example, boron serving as a p-type impurity is generally implanted into a channel region. This boron diffuses out toward a silicon oxide film embedded in the trench and a silicon oxide film formed by rounding the upper corner portion of the trench, and hence the boron concentration is reduced in the upper corner portion of the trench. Consequently, the threshold voltage is partially reduced in the upper corner portion of the trench.
For example, Japanese Patent Laying-Open No. 2000-150878 discloses a technique for suppressing reduction of a threshold voltage resulting from diffusion of an impurity. In a method of fabricating a semiconductor device proposed in this gazette, a trench for element isolation is first formed on a semiconductor substrate. An impurity of the same conductivity type as that for forming a channel region is obliquely ion-implanted into the main surface of the semiconductor substrate. Thus, the impurity sufficiently remains in the edge of the channel region (the upper corner portion of the trench) even upon out diffusion of the impurity, and hence reduction of the threshold voltage can be suppressed.
However, this proposed technique has the following problems:
Consider that the aforementioned proposed technique is applied to a CMOS transistor having a first conductivity type channel region and a second conductivity type channel region on a substrate. In this case, when the first conductivity type impurity is ion-implanted into the first conductivity type channel region, an ion implantation mask such as a resist mask must be formed on the second conductivity type channel region, in order to ion-implant impurities of the same conductivity types as the channel regions.
However, an end of the ion implantation mask blocks the impurity when the same is obliquely implanted into the channel region located on the inner side surface of the trench through the ion implantation mask. Thus, it is difficult to sufficiently implant the impurity into the channel region. In other words, it is difficult to implant the impurity into the channel region when the ion implantation mask shades the channel region. Particularly when elements are refined, the end of the ion implantation mask so approaches the channel region subjected to ion implantation that the channel region is readily shaded by the ion implantation mask.
The impurity may alternatively be implanted into the overall surface of the trench without through the ion implantation mask. However, when first conductivity type impurity ions are implanted into the overall surface of the trench in order to suppress reduction of the threshold voltage caused by diffusion of the impurity in the upper corner portion of the first conductivity type channel region, for example, the first conductivity type impurity is inevitably also implanted into the second conductivity type channel region. In the upper corner portion of the second conductivity type channel region, therefore, the action of the impurity is canceled and the threshold voltage is reduced. Consequently, a leakage current disadvantageously readily flows through the portion having the reduced threshold voltage.
As hereinabove described, it is generally difficult to suppress fluctuation of the threshold voltage in the upper corner potion of the trench isolating the first conductivity type channel region and the second conductivity type channel region from each other.
SUMMARY OF THE INVENTION
An object of the present invention is to provide a method of fabricating a semiconductor device capable of suppressing fluctuation of a threshold voltage in an upper corner portion of a trench isolating a first conductivity type channel region and a second conductivity type channel region from each other.
Another object of the present invention is to reliably introduce a first impurity into the upper corner portion of the trench in the aforementioned method of fabricating a semiconductor device.
A method according to a first aspect of the present invention is a method of fabricating a semiconductor device including a first transistor having a first conductivity type channel region and a second transistor having a second conductivity type channel region, comprising steps of forming a trench for isolating the first transistor and the second transistor from each other on a semiconductor substrate, rounding upper corner portions of the trench by thermal oxidation, introducing a first impurity into both upper corner portions of the trench, introducing a second impurity into a region for defining the first conductivity type channel region, introducing a third impurity into a region for defining the second conductivity type channel region and heat-treating the semiconductor substrate. According to the present invention, the term “semiconductor substrate” indicates a wide concept including not only an ordinary semiconductor substrate but also a semiconductor layer formed on an insulating substrate or the like.
In the method of fabricating a semiconductor device according to the first aspect, the first impurity is introduced into both upper corner portions of the trench after rounding the upper corner portions of the trench by thermal oxidation as described above, whereby the threshold voltage in the upper corner potion of the trench can be previously increased by rounding oxidation and introduction of a p-type impurity in an n-channel transistor when employing the p-type impurity as the first impu
Oda Masahiro
Sasada Kazuhiro
Cuneo Kamand
McDermott & Will & Emery
Sanyo Electric Co,. Ltd.
Sarkar Asok Kumar
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