Method of fabricating semiconductor device having dual gate

Details Method of fabricating semiconductor device having dual gate Method of fabricating semiconductor device having dual gate

2011-07-05

2011-07-05

Garber, Charles D (Department: 2812)

Semiconductor device manufacturing: process

Coating with electrically or thermally conductive material

Insulated gate formation

C438S216000, C438S275000, C438S287000

Reexamination Certificate

active

07972950

ABSTRACT:
A method of fabricating a semiconductor device having a dual gate allows for the gates to have a wide variety of threshold voltages. The method includes forming a gate insulation layer, a first capping layer, and a barrier layer in the foregoing sequence across a first region and a second region on a substrate, exposing the gate insulation layer on the first region by removing the first capping layer and the barrier layer from the first region, forming a second capping layer on the gate insulation layer in the first region and on the barrier layer in the second region, and thermally processing the substrate on which the second capping layer is formed. The thermal processing causes material of the second capping layer to spread into the gate insulation layer in the first region and material of the first capping layer to spread into the gate insulation layer in the second region. Thus, devices having different threshold voltages can be formed in the first and second regions.

REFERENCES:
patent: 7030001 (2006-04-01), Adetutu et al.
patent: 7084024 (2006-08-01), Gluschenkov et al.
patent: 7291526 (2007-11-01), Li
patent: 7504700 (2009-03-01), Zhu et al.
patent: 7601577 (2009-10-01), Chambers et al.
patent: 2003/0180994 (2003-09-01), Polishchuk et al.
patent: 2006/0237803 (2006-10-01), Zhu et al.
patent: 2007/0048920 (2007-03-01), Song et al.
patent: 2008/0283929 (2008-11-01), Nabatame
patent: 1020050045737 (2005-05-01), None
patent: 1020070078975 (2007-08-01), None
T. Schram et al, “Novel process to pattern selectively dual dielectric capping layers using soft-mask only,” 17-19 Junge 2008, 2008 Symposium on VLSI Technology p. 44-45.
Ragnarsson, Lars-Ake et al, “Achieving conduction band-edge effective work functions by La2O3 capping of hafnium silicates,” Jun. 2007, IEEE Electron Device Letters, vol. 28 No. 6 p. 486-488.

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