Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-09
2003-04-08
Chaudhuri, Olik (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S304000, C438S305000, C438S519000
Reexamination Certificate
active
06544849
ABSTRACT:
CROSS-REFERENCE TO RELATED APPLICATION
This application claims the priority benefit of Taiwan application serial no. 90110251, filed on Apr. 30, 2001.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a semiconductor device. More particularly, the invention relates to a method of fabricating the semiconductor device for preventing polysilicon lines from being damaged during removal of a photoresist layer.
2. Description of the Related Art
The input signals to a metal-oxide semiconductor integrated circuit (MOS IC) are usually fed to the gates of MOS transistors. If the voltage applied to the gate insulator becomes excessive, the gate oxide can break down. The main source of such voltages is triboelectricity (electricity caused when two materials are rubbed together). A person can develop a very high static voltage simply by walking across a room, and so as the process of removing an integrated circuit from its plastic package can. If such a high voltage is accidentally applied to pins of an IC package, its discharge (referred to as electrostatic discharge, ESD) can cause breakdown of the gate oxide of the devices to which it is applied, or even a device failure. Therefore, to prevent damage by electrostatic discharge, an electrostatic discharge protection device is often designed in a device or an integrated circuit.
The electrostatic discharge protection device may include a so-called node-to node punch-through electrostatic discharge protection device. The node-to-node punch-through electrostatic discharge protection device is often applied to a complementary metal-oxide semiconductor circuit. The fabrication process comprises implanting arsenic ions or phosphoric ions into a substrate after a polysilicon gate is formed and patterned. In the conventional fabrication process, polysilicon gates of a core transistor in a core device area and an I/O transistor (including a transistor for making the electrostatic discharge protection device) in a peripheral area are often patterned simultaneously. When an ion implantation is performed on the electrostatic discharge protection device, a photoresist layer is formed to cover the core device, exposing only two sides of the polysilicon gate of the I/O transistor to be implanted. After the ion implantation is performed, the photoresist layer is stripped. The method of stripping the photoresist layer includes an oxygen plasma ashing at a temperature of about 200° C. to about 300° C. With the photoresist layer covers the whole core device, implying that the photoresist layer having a large area, a significant thermal stress is caused when the photoresist layer is stripped using the oxygen plasma. As a result, the gate of the core transistor would be broken.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a semiconductor, to prevent a polysilicon line from being damaged during removal of the photoresist layer.
As embodied herein, the invention provides a method of fabricating the semiconductor device for preventing polysilicon line from being damaged during removal of a photoresist layer. The method begins by forming polysilicon lines on a core device region and an electrostatic discharge protection device region of a substrate. A plurality of offset spacers is formed on sidewalls of the polysilicon lines. After the offset spacers are formed, a photoresist layer is formed over the substrate to cover the core device region, while exposing the electrostatic discharge protection device region. With the photoresist layer serving as a mask, a punch-through ion implantation is performed on the electrostatic discharge protection device region before the photoresist layer is removed. Next, a plurality of lightly doped source/drain regions is formed in the core device region. A plurality of spacers is further formed on the edge of the offset spacers, followed by forming source/drain regions in the core device region and the electrostatic discharge protection device.
Since the offset spacers are formed on the sidewalls of the polysilicon lines before the photoresist layer is removed, the offset spacers can protect the polysilicon line from being broken.
According to the present invention, the drawback of breaking the polysilicon gate can be avoided, while providing advantages of forming the offset spacer, such as preventing the dopant of a lightly doped drain region formed subsequently from diffusing towards the substrate under the gate. Thus, this reduces a gate-to-substrate overlap capacitance, so as to improve the AC performance of the device. As the problems of gate breakage and the gate-to-substrate overlap capacitance are resolved, the invention can be applied to the gate having a smaller linewidth, for example, to the gate of a core transistor with a width of 0.1 micron.
In addition to avoid the gate-to-substrate overlap capacitance as mentioned above, the offset spacer can also be used to adjust the channel length. For example, when a channel length of 0.31 micron is to be formed, the width of the offset spacer can be adjusted to result in a channel length of 0.31 micron as required by specification, even if the gate only has a width of 0.29 micron.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 5618740 (1997-04-01), Huang
patent: 5998274 (1999-12-01), Akram et al.
patent: 6121090 (2000-09-01), Wu
Hsu Shih-Chieh
Huang Chang-Chi
Huang Cheng-Tung
Lin Sheng-Hao
Sheng Yi-Chung
Chaudhuri Olik
Lee Hsien Ming
United Microelectronics Corp.
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