Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-05-04
2002-12-10
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S669000
Reexamination Certificate
active
06492223
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device which is equipped with a capacitor portion, and in particular, to a method of fabricating a semiconductor device, such as a semiconductor integrated circuit or the like, which is equipped with a capacitor portion.
2. Description of the Related Art
In semiconductor devices, and in analog circuits and RF (radio frequency) circuits in particular, a capacitor portion is an indispensable element. Conventionally, semiconductor devices, such as semiconductor integrated circuits, equipped with a capacitor portion have been structured as follows.
As illustrated in
FIG. 8
, underlayer wiring patterns
101
A,
101
B are formed on a semiconductor substrate
100
. An insulating film layer
103
is formed on the underlayer wiring patterns
101
A,
101
B. At the insulating film layer
103
are formed a lower electrode
105
, which is one electrode of a capacitor portion, and vias
104
A,
104
B for connecting a wire
107
B for leading an electrode and the like. The lower electrode
105
is provided above (i.e., at the upper side of in
FIG. 8
) the vias
104
A. The lower electrode
105
is connected to the vias
104
A and the underlayer wiring pattern
101
A, and to the wire
107
B for leading an electrode via the via
104
B. Moreover, a capacitor insulating film pattern
106
is formed so as to cover the lower electrode
105
. An upper electrode
108
is provided on the capacitor insulating film pattern
106
.
Such a conventional semiconductor device equipped with a capacitor portion is fabricated as follows.
First, an underlayer wiring layer is formed on the semiconductor substrate
100
. The underlayer wiring patterns
108
,
101
B are formed by photolithography and etching processing. Next, the insulating film layer
103
is deposited on the underlayer wiring patterns
101
A, to
101
B. Thereafter, openings are formed in the insulating film layer
103
. Tungsten or the like is filled into these openings so as to form the vias
104
A,
104
B.
Next, a metal layer is deposited. This metal layer is worked into a desired pattern by photolithography and etching processing, so as to form the lower electrode
105
. Then, a capacitor insulating film layer is deposited, and is worked by photolithography and etching processing so as to form the capacitor insulating film pattern
106
to cover the lower electrode
105
. At this time, the via
104
B is exposed. Finally, a predetermined metal layer is layered thereon, and is worked by photolithography and etching processing so as to form the upper electrode
108
and the wirings
107
A,
107
B for leading an electrode.
Moreover, the semiconductor device equipped with a capacitor portion which is illustrated in
FIG. 9
is known. The lower electrode
105
, which is one electrode of a capacitor portion, is formed on the semiconductor substrate
100
. The insulating film layer
103
is formed at both end portions of the lower electrode
105
. The capacitor insulating film pattern
106
is formed on the insulating film layer
103
so as to cover the lower electrode
105
and the insulating film layer
103
. Further, the upper electrode
108
is formed on the capacitor insulating film pattern
106
so as to cover the entire capacitor insulating film layer
106
.
The semiconductor device equipped with a capacitor portion which is illustrated in
FIG. 10H
is also known. A metal layer
109
, which becomes the lower electrode
105
, is formed on the substrate
100
(see FIG.
10
A). A resist pattern
102
is formed on the metal layer
109
(see FIG.
10
B). The metal layer
109
is etched by using the resist pattern
102
as a mask, such that the lower electrode
105
is formed. The metal layer
109
which is to become the lower electrode
105
has a structure in which are layered a 100 nm Ti/TiN film (serving as a barrier metal) as the lowermost layer, and next, a 500 nm Al—Si—Cu (Si 3%, Cu 1%) film, and a 100 nm Ti/TiN film (for the purpose of preventing reflection) as the uppermost layer.
Thereon, a 100 nm CVD oxide film which is to become the capacitor insulating film pattern
106
is layered. A 100 nm Ti/TiN film, which serves as a metal layer
109
B which is to become the upper electrode
108
, is layered on the capacitor insulating film pattern
106
(see FIG.
10
D). Then, the resist pattern
102
is formed thereon (see FIG.
10
E). The metal layer
109
B is etched by using the resist pattern
102
as a mask, so as to form the upper electrode
108
(see FIG.
10
F).
Thereafter, an insulating film layer
110
serving as an inter-layer insulating layer is formed on the entire wafer surface. Planarizing (flattening) by CMP (chemical mechanical polishing) is carried out (see FIG.
10
G), and an inter-layer film cap insulating film
111
is formed. The vias
104
are formed by photolithography and etching processing, and thereon, a metal layer
113
which supports the upper electrode is layered.
However, in the conventional methods for fabricating a semiconductor device equipped with a capacitor portion, the formation of the pattern of the lower electrode
105
by photolithography and etching processing, and the formation of the pattern of the capacitor insulating film
106
by photolithography and etching processing, are carried out independent of one another. Thus, there are drawbacks in that there are many processing steps, work is complicated, and costs increase.
Further, the capacitor insulating film pattern
106
which covers the end portions of the lower electrode
105
deteriorates (portion A in FIG.
8
and portion C in FIG.
9
), and an electric field concentrates at a portion of the upper electrode
108
such that the breakdown voltage of the capacitor insulating film pattern
106
deteriorates (portion A in FIG.
8
). In addition, due to the effect of the step formed by the underlayer wiring pattern
101
A, the lower electrode
105
cannot be planarized well even if CMP is carried out, and there is the possibility that weak spots may arise in the capacitor insulating film pattern. Moreover, when the vias
104
A are formed, a step is formed, and as a result, the flatness of the lower electrode
105
deteriorates, such that weak spots arise in the capacitor insulating film pattern. Due to this deterioration of properties, deterioration in breakdown voltage, and generation of weak spots, it is difficult for the capacitor insulating film pattern
106
to be made thin. A problem arises in that the capacity per unit surface area cannot be made large, which impedes the ability to make the semiconductor device more highly integrated.
Moreover, after formation of the lower electrode
105
and the capacitor insulating film pattern
106
, the upper electrode
108
and the like are formed. Thus, at the stepped portions (portion B in
FIG. 8
, portion C in
FIG. 9
, and portion D in
FIGS. 10F through 10H
) of the end portions of the capacitor insulating film pattern
106
, it is easy for metal wire remains
120
(see
FIG. 10
) at the time of etching processing to be generated. Problems arise such as these remains are a cause of short circuits occurring between adjacent patterns such that the reliability deteriorates.
SUMMARY OF THE INVENTION
The present invention was formed in order to overcome the above-described problems, and objects of the present invention are to provide a semiconductor device in which it is difficult for metal wire remains to be generated and in which reliability is improved, and to prevent a deterioration in breakdown voltage of a capacitor portion and aim for an increase in integration of semiconductor elements, and to decrease the number of fabrication processes so as to reduce costs.
In order to achieve the above object, a first aspect of the present invention is a method of fabricating a semiconductor device equipped with a capacitor portion, the method comprising the steps of: successively layering, on a substrate, a first metal layer which becomes a lower electrode and a wiring pattern, an ins
Kanamori Jun
Katakura Yoshiaki
Chaudhari Chandra
Oki Electric Industry Co, Ltd.
Rabin & Berdo P.C.
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