Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1993-07-19
2003-04-08
Trinh, Michael (Department: 2822)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S299000, C438S671000
Reexamination Certificate
active
06544852
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a production method for forming a self-aligned contact in a MOS-type semiconductor device.
2. Description of the Related Art
FIG. 3
is a sectional view of a conventional semiconductor device having a gate electrode
24
, a wiring layer
36
, and so forth. A contact hole
33
is formed by effecting positioning by photo-lithography after an inter-level insulating film
35
is formed. Therefore, a margin comprising the sum of a positioning error &dgr; and variance &lgr; at the time of etching must always be taken into consideration. Assuming that the distance between the edge of the gate electrode
24
and the edge of a contact hole
33
is n, for example, the relation n>&dgr;+&lgr; must be satisfied. This is a great obstacle when a semiconductor device is miniaturized. In a 0.8 &mgr;m rule, for example, &dgr;=0.4 &mgr;m and &lgr;=0.2 &mgr;m; hence, n>0.6 &mgr;m. From the aspect of a process margin, n must be about 0.8 &mgr;m.
It is thus desirable to reduce the size of a semiconductor device by reducing as much as possible the distance n between the edge of the contact hole and the gate electrode described above and the distance p between the contact hole and a device isolation layer
22
.
SUMMARY OF THE INVENTION
It is an object of the present invention to provide a method of fabricating a MOS device comprising forming a gate insulating film on a semiconductor substrate, forming a gate electrode film on the gate insulating film, forming a first insulating film on the gate electrode film, patterning the gate electrode film and the first insulating film by using a first patterned photoresist film as a mask, forming impurity source and drain layers in the semiconductor substrate by using the patterned gate electrode film as a mask, forming a second insulating film on the exposed surface of the gate insulating film and the first insulating film, etching the second insulating film to form a side wall insulating film on the side wall of the gate electrode and to expose a surface of the semiconductor substrate, forming a conductor film on the exposed surface of the semiconductor substrate, the first insulating film and the side wall insulating film, and patterning the conductor film in a desired shape.
Another object of the invention is to provide a method of fabricating a MOS device comprising forming a gate insulating film on a semiconductor substrate, forming a gate electrode film on the gate insulating film, forming a first insulating film on the gate electrode film, patterning the gate electrode film and the first insulating film by using a first patterned photoresist film as a mask, forming impurity source and drain layers on a face of the semiconductor substrate by using the patterned gate electrode film as a mask, forming a second insulating film on the exposed surface of the gate insulating film and the first insulating film, etching the second insulating film to form a side wall insulating film on the side wall of the gate electrode and to expose a surface of the semiconductor substrate, forming a conductor film on the exposed surface of the semiconductor substrate, the first insulating film and the side wall insulating film, forming a film having a flattening face on the conductor film, and etching a region of the flattened film and the conductor film in the region above the gate electrode film, using a second patterned photoresist film as a mask.
After the gate electrode film and the insulating film disposed on the gate electrode film are simultaneously etched and patterned, a side wall insulating film is formed on the side wall of the gate electrode film by an etch-back method. A conductor film is then formed so as to bring impurity source and drain layers into direct contact with the conductor film, and thereafter the conductor film is patterned in a desired shape.
Since the gate electrode is covered with the upper insulating film and the side wall insulating film, the conductor film can be formed over them in contact with impurity source and drain layers without using an inter-level insulating film which is used in the prior art. As a result, since a mask for forming a contact is not necessary, the semiconductor device can be miniaturized.
According to the present invention, the above-mentioned problems are solved by utilizing the fact that the vicinity of the gate electrode is higher than other regions of the device. That is, after the conductor film is formed, a flattening film is deposited to flatten the surface of the semiconductor device, and the conductor film on the gate electrode is then patterned only over a region that is to be etched.
The flattening film on the gate electrode film is etched, and then the conductor film is etched. The conductor film on the gate electrode film is higher than on other regions, and therefore the conductor film on the gate electrode film is etched preferentially.
After the gate electrode film and a silicon nitride film disposed on the gate electrode film are simultaneously etched and patterned, a silicon nitride film is formed on the side wall of the gate electrode film by an etch-back method, a conductor film is then formed so as to bring impurity source and drain layers into direct contact with the conductor film, and thereafter the conductor film is patterned in a desired shape.
Since the gate electrode is covered with the upper silicon nitride film and the side wall silicon nitride film, the conductor film can be formed over them in contact with impurity source and drain layers without using an inter-level insulating film. Again, since a mask for forming a contact is not necessary, the semiconductor device can be miniaturized.
REFERENCES:
patent: 4735916 (1988-04-01), Homma et al.
patent: 4810666 (1989-03-01), Taji
patent: 4849369 (1989-07-01), Jeuch et al.
patent: 4902640 (1990-02-01), Sachitano et al.
patent: 4992389 (1991-02-01), Ogura et al.
patent: 4994402 (1991-02-01), Chiu
patent: 5010039 (1991-04-01), Ku et al.
patent: 5015598 (1991-05-01), Verhaar
patent: 5022958 (1991-06-01), Farreau et al.
patent: 5180689 (1993-01-01), Liu et al.
patent: 5236851 (1993-08-01), Kameyama et al.
patent: 0276271 (1988-11-01), None
patent: 0110772 (1989-04-01), None
Ghandhi, VLSI Fabrication Principles, pp 534-538, 542-548, 1983.
Adams & Wilks
Seiko Instruments Inc.
Trinh Michael
LandOfFree
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