Active solid-state devices (e.g. – transistors – solid-state diode – Field effect device – Having insulated electrode
Reexamination Certificate
2001-09-21
2002-06-25
Smith, Matthew (Department: 2825)
Active solid-state devices (e.g., transistors, solid-state diode
Field effect device
Having insulated electrode
C257S341000, C257S342000, C438S270000, C438S212000, C438S268000
Reexamination Certificate
active
06410959
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a semiconductor device and, more particularly, to an art which can be usefully applied to a semiconductor device having a transistor element of trench gate structure.
BACKGROUND OF THE INVENTION
Power transistors (semiconductor devices) are used as switching elements for power amplification circuits, power supply circuits and the like. This kind of power transistors has a construction in which a plurality of transistor elements are electrically connected in parallel. Each of the transistor elements is constructed as, for example, a MISFET (Metal Insulator Semiconductor Field Effect Transistor) of trench gate structure. A method of fabricating a power transistor having a MISFET of trench gate structure will be described below.
First, an n
+
-type semiconductor layer is formed over a major surface of an n
−
-type semiconductor substrate made of single-crystal silicon by an epitaxial growth method. These n
+
-type semiconductor substrate and n
−
-type semiconductor layer are used as a drain region. Then, p-type impurities are introduced into the entire major surface of the n
−
-type semiconductor layer by ion implantation to form a p-type semiconductor region to be used as a channel forming region. Then, n-type impurities are selectively introduced into the major surface of the p-type semiconductor region by ion implantation to form an n
+
-type semiconductor region which serves as a source region.
Then, after, for example, a silicon oxide film has been formed over the major surface of the n
−
-type semiconductor layer, patterning is applied to the silicon oxide film to form a mask having an opening above a trench forming region of the n
−
-type semiconductor layer. Then, a trench is formed from the major surface of the n
−
-type semiconductor layer in the depth direction thereof by using the mask as an etching mask. The formation of the trench is performed by an anisotropic dry etching method.
Then, wet etching is applied to allow the mask to recede from the top edge portion of the trench (the portion of intersection of the side surface of the trench and the major surface of the n
−
-type semiconductor layer). Then, isotropic dry etching is applied to form the top edge portion and the bottom edge portion (the portion of intersection of the side surface of the trench and the bottom surface thereof) of the trench into gently-sloping shapes, respectively. Then, the mask is removed.
Then, thermal oxidation is applied to form a sacrifice thermal oxide film over the internal surface of the trench, and then the sacrifice thermal oxide film is removed. The formation and the removal of the sacrifice thermal oxide film are performed for the purpose of removing defects, strain, contamination and the like which are produced when the trench is formed.
Then, thermal oxidation is applied to form a gate insulating film comprising a thermal oxide film over the internal surface of the trench. Then, a polycrystalline silicon film is formed over the entire major surface of the n
−
-type semiconductor layer, inclusive of the inside of the trench, by a chemical vapor deposition method. Impurities for decreasing the resistance value of the polycrystalline silicon film are introduced into the polycrystalline silicon film during or after the deposition thereof.
Then, etchback is applied to flatten the surface of the polycrystalline silicon film. Then, etching is selectively applied to the polycrystalline silicon film to form a gate electrode in the trench and to form a gate lead-out electrode integrated with the gate electrode, over the peripheral region of the major surface of the n
−
-type semiconductor layer. In this step, a MISFET is formed which has a trench gate structure in which the gate electrode is formed in the trench of the n
−
-type semiconductor layer, with the gate insulating film interposed therebetween.
Then, an interlayer insulating film is formed over the entire major surface of the n
−
-type semiconductor layer, inclusive of the top surface of the gate electrode, and then a contact hole is formed in the interlayer insulation film. After that, a source interconnection and a gate interconnection are formed, and then a final passivation film is formed. After that, a bonding opening is formed in the final passivation film, and then a drain electrode is formed on the back of the n
+
-type semiconductor substrate, whereby a power transistor having such a MISFET of trench gate structure is almost finished.
The MISFET having the trench gate structure constructed in this manner can be reduced in its occupation area compared to a MISFET in which its gate electrode is formed on the major surface of its semiconductor layer, with a gate insulating film interposed therebetween. Accordingly, the size and on resistance of the power transistor can be reduced.
Incidentally, a power transistor having a MISFET of trench gate structure is described in, for example, EP 666,590.
SUMMARY OF THE INVENTION
The present inventors have examined the above-described power transistor (semiconductor device) and found out the following problems.
In the case of the above-described power transistor, the p-type semiconductor region which serves as the channel forming region is formed in the n
−
-type semiconductor layer which serves as the drain region, and the n
+
-type semiconductor region which serves as the source region is formed in the p-type semiconductor region, and after the trench has been formed in the n
−
-type semiconductor layer, thermal oxidation is applied to form the thermal oxide film which serves as the gate insulating film, over the internal surface of the trench. Therefore, impurities in the p-type semiconductor region (for example, boron (B)) or impurities of the n
+
-type semiconductor region (for example, arsenic (As)
l
) is introduced into the thermal oxide film and the breakdown voltage of the gate insulating film becomes easily degraded, so that the reliability of the power transistor lowers.
Further, impurities in the p-type semiconductor region at the side surface of the trench migrate into the thermal oxide film and a variation occurs in the impurity concentration in the channel forming region at the side surface of the trench, so that a variation occurs in the threshold voltage (Vth) of the MISFET and FET characteristics cannot be provided stably with good reproducibilty.
In addition, impurities of the n
+
-type semiconductor region which serves as the source region undergo enhanced diffusion by the thermal treatment temperature during the formation of the thermal oxide film, and the effective channel length of the MISFET is shortened and the punch-through breakdown voltage thereof is lowered. If the thermal oxide film is formed at a low thermal treatment temperature of approximately 950° C., enhanced diffusion of impurities in the n
+
-type semiconductor substrate which serves as the source region can be suppressed and the punch-through breakdown voltage of the MISFET can be ensured. However, if the thermal oxide film is formed at such a low thermal treatment temperature, the top edge portion of the trench is deformed into an angular shape by a compressive stress produced during the growth of the thermal oxide film, the film thickness of the thermal oxide film at the top edge portion becomes locally thin, so that the gate breakdown voltage of the MISFET is lowered. Therefore, if the thermal oxide film is formed at a high thermal treatment temperature of approximately 1,100° C., the deformation of the top edge portion of the trench can be suppressed and the gate breakdown voltage of the MISFET can be ensured. However, if the thermal oxide film is formed at a high thermal treatment temperature of approximately 1,100° C., as described above, impurities in the n
+
-type semiconductor substrate which serves as the source region undergo enhanced diffusion and the punch-through breakdown voltage of the MISFET is lowere
Imai Yasuo
Kobayashi Masayoshi
Kubo Sakae
Kudo Satoshi
Nakazawa Yoshito
Hitachi , Ltd.
Keshavan B. V.
Smith Matthew
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