Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

2000-09-13

2002-04-09

Nelms, David (Department: 2818)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S257000, C438S303000

Reexamination Certificate

active

06368907

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device containing a nonvolatile memory device and a logic device.
In fabrication of a semiconductor device containing both a nonvolatile memory device (PROM memory cells) and a logic device (CMOS transistors), a method in which improvement in reliability of the nonvolatile memory device and high performance of the logic device can be both realized is recently desired.
A conventional method of fabricating such a semiconductor device containing both of these devices will now be described with reference to drawings.
FIGS.
12
(
a
) through
12
(
d
),
13
(
a
) through
13
(
d
),
14
(
a
) through
14
(
d
),
15
(
a
) through
15
(
d
) and
16
(
a
) through
16
(
c
) are sectional views for showing procedures in the conventional method of fabricating a semiconductor device. In each of these drawings, Rmemo indicates a memory region where a nonvolatile memory device is to be formed, Rlogc indicates a logic region where a logic device (including P-channel and N-channel transistors) is to be formed, a reference numeral
101
denotes a silicon substrate of P-type monosilicon, a reference numeral
102
denotes an isolation insulating film of a silicon oxide film, a reference numeral
103
denotes a first implant protection film of a silicon oxide film, a reference numeral
105
denotes an N-type well, a reference numeral
107
denotes a p-type well, a reference numeral
108
denotes a gate insulating film of the nonvolatile memory device, a reference numeral
109
denotes a first polysilicon film, a reference numeral
110
denotes an ONO film (a laminated film including an oxide film, a nitride film and an oxide film), a reference numeral
114
denotes a gate insulating film of the logic device, a reference numeral
115
denotes a second polysilicon film, a reference numeral
117
denotes a control gate electrode of the nonvolatile memory device, a reference numeral
118
denotes an interelectrode insulating film of the nonvolatile memory device, a reference numeral
119
denotes a floating gate electrode of the nonvolatile memory device, a reference numeral
121
denotes a gate electrode of the logic device, a reference numeral
122
denotes a second implant protection film, a reference numeral
124
denotes a source/drain diffusion layer of the nonvolatile memory device, a reference numeral
126
denotes an LDD diffusion layer of the N-channel transistor, a reference numeral
128
denotes an LDD diffusion layer of the P-channel transistor, a reference numeral
129
denotes a sidewall spacer of the nonvolatile memory device and the logic device, a reference numeral
131
denotes a source/drain diffusion layer of the N-channel transistor, a reference numeral
133
denotes a source/drain diffusion layer of the P-channel transistor, and reference numerals
104
,
106
,
111
,
112
,
113
,
116
,
120
,
123
,
125
,
127
,
130
and
132
denote masks of photoresist films for use in ion implantation or etching.
First, in the procedure shown in FIG.
12
(
a
), an isolation insulating film
102
of a silicon oxide film is formed in the memory region Rmemo and the logic region Rlogc on a silicon substrate
101
, and a first implant protection film
103
of a silicon oxide film is then formed in a region surrounded with the isolation insulating film
102
on the silicon substrate
101
.
Next, in the procedure shown in FIG.
12
(
b
), an N-type well
105
is formed in the silicon substrate
101
by implanting ions of an N-type impurity (such as phosphorus) into a P-channel transistor formation region of the logic region Rlogc by using an N-type well formation mask
104
for covering the memory region Rmemo and an N-channel transistor formation region of the logic region Rlogc.
Then, in the procedure shown in FIG.
12
(
c
), after removing the N-type well formation mask
104
, a P-type well
107
is formed in the silicon substrate
101
by implanting ions of a P-type impurity (such as boron) into the entire memory region Rmemo and the N-channel transistor formation region of the logic region Rlogc by using a P-type well formation mask
106
for covering the P-channel transistor formation region of the logic region Rlogc. At the same time, impurity ions are implanted into the silicon substrate
101
by using the P-type well formation mask
106
for controlling the threshold values of the nonvolatile memory device and the N-channel transistor.
Next, in the procedure shown in FIG.
12
(
d
), after removing the P-type well formation mask
106
, the first implant protection film
103
in both the memory region Rmemo and the logic region Rlogc is removed by wet etching using buffered hydrofluoric acid.
Subsequently, in the procedure shown in FIG.
13
(
a
), a gate insulating film
108
of a silicon oxide film of the nonvolatile memory device is formed in the memory region Rmemo and the logic region Rlogc by thermal oxidation, and a first polysilicon film
109
including phosphorus is then formed by CVD. The first polysilicon film
109
is to be formed into a floating gate electrode of the nonvolatile memory device. Thereafter, the first polysilicon film
109
is patterned by using a mask not shown so as to determine the dimension along the channel width of the nonvolatile memory device. Then, after removing the mask for patterning the first polysilicon film
109
, an ON film
110
a
(a laminated film including an oxide film and a nitride film) to be formed into an interelectrode insulating film of the nonvolatile memory device is formed by the CVD.
Next, in the procedure shown in FIG.
13
(
b
), the ON film
110
a
and the first polysilicon film
109
in the logic region Rlogc are successively removed by the dry etching using a mask
111
for covering the entire memory region Rmemo.
Then, in the procedure shown in FIG.
13
(
c
), phosphorus ions (P
+
) are implanted for controlling the threshold value of the P-channel transistor in the logic region Rlogc by using a threshold controlling implantation mask
112
for covering the entire memory region Rmemo and the N-channel transistor formation region of the logic region Rlogc with the gate insulating film
108
remaining after the dry etching used as an implant protection film.
Next, in the procedure shown in FIG.
13
(
d
), after removing the threshold control implantation mask
112
, boron ions (B
+
) are implanted for controlling the threshold value of the N-channel transistor in the logic region Rlogc by using a threshold controlling implantation mask
113
for covering the memory region Rmemo and the P-channel transistor formation region of the logic region Rlogc with the gate insulating film
108
used as an implant protection film.
Then, in the procedure shown in FIG.
14
(
a
), after removing the threshold controlling implantation mask
113
, the gate insulating film
108
remaining in the logic region Rlogc is removed by the wet etching using buffered hydrofluoric acid.
Next, in the procedure shown in FIG.
14
(
b
), a gate insulating film
114
of a silicon oxide film of the logic device is formed by the thermal oxidation. At this point, the surface of the ON film
110
a
in the memory region Rmemo is also oxidized into an ONO film
110
. Then, a second polysilicon film
15
including phosphorus to be formed into a control gate electrode of the nonvolatile memory device and a gate electrode of the logic device is formed by the CVD.
Then, in the procedure shown in FIG.
14
(
c
), the second polysilicon film
115
, the first insulating film
110
and the first polysilicon film
109
in the memory region Rmemo are successively patterned by the dry etching using a stacked gate formation mask
116
for covering the entire logic region Rlogc and a gate formation region of the memory region Rmemo, so as to form a stacked gate of the nonvolatile memory device including a control gate electrode
117
, an interelectrode insulating film
118
and a floating gate electrode
119
.
Next, in the procedure shown in FIG.
14
(
d
), after removing

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