Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-07-03
2002-08-13
Dang, Trung (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S238000, C438S240000, C438S381000
Reexamination Certificate
active
06432767
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to a semiconductor device having capacitors using a ferroelectric film such as ferroelectric nonvolatile memory of a dynamic random access memory (DRAM).
Some ferroelectric materials have extremely large relative dielectric constants ranging from several hundreds to several thousands. Therefore, use of a thin film made of these ferroelectric materials for a capacitor dielectrics provides a capacitor of small area and large capacity suitable for large scale integration (LSI) devices. Also, the ferroelectric material has spontaneous polarization that can be inverted in direction by an applied electric field, thereby providing a nonvolatile memory.
As described in Japanese unexamined Patent Application No. 5-90606 and referring to
FIG. 14
, the conventional ferroelectric memory is fabricated by forming on an interlayer insulating film
144
with a bottom Pt electrode
145
, ferroelectric film
146
, and a top Pt electrode
147
in this order, thereby forming a ferroelectric capacitor. However, in the conventional ferroelectric memory, each of the layers is formed with an independent mask, which makes the memory cell area large because of critical dimension uniformity and alignment tolerance, thereby making it difficult to fabricate highly integrated memory devices. The conventional technique also involves a problem of thinning the interlayer insulating film
144
for the conventional technique repeats the patterning on it for forming the ferroelectric capacitors.
To solve the above-mentioned problems, a method was proposed as described in Japanese unexamined Patent Application No. 2-288368, in which a top electrode
158
, a ferroelectric film
157
, and a bottom electrode
156
are collectively dry-etched with the photoresist used as a mask as shown in FIG.
15
. This method uses polysilicon for the top and bottom electrodes
158
and
156
, which are dry-etched with C
2
Cl
2
F
4
, SF
6
, and Ar gases.
However, forming a ferroelectric film directly on polysilicon, a silicon oxide film of a low dielectric constant is formed at the interface. The silicon oxide film thus formed significantly deteriorates capacitor characteristics. To avoid this deterioration, it is necessary to use electrodes made of noble metals such as platinum and palladium or conductive oxides such as IrO
2
, RuO
2
, and ReO
3
.
Of the above-mentioned electrode materials, platinum is considered best suited for the application. Therefore, in the memory cell forming process described in Japanese unexamined Patent Application No. 5-299601 collectively dry-etches a top electrode
45
, a ferroelectric film
44
, a bottom electrode
43
, and a conductive diffusion barrier layer
169
with the photoresist used as the mask as shown in FIG.
16
. Use of such a structure can implement microscopic capacitors without losing their properties.
Actually, however, platinum cannot be converted to a highly volatile reaction product to be dry-etched. It was observed that, if platinum is dry-etched, a redeposited material forms a wall-shaped residue (hereinafter referred to as a platinum-contained deposit) on the capacitor side wall due to the low volatility. In this structure, the above-mentioned platinum-contained deposits short-circuit the top electrode
45
and the bottom electrode
43
.
It is therefore an object of the present invention to provide a capacitor in which the top and bottom electrodes thereof will not be short-circuited when the top electrode, the ferroelectric film, and the bottom electrode are etched with single photolithography process step.
SUMMARY OF THE INVENTION
This object is achieved by setting the taper angle of the side wall of the ferroelectric film constituting the ferroelectric capacitor to less than 75 degrees to the main surface of the substrate on which the ferroelectric capacitor is formed. That is, the taper angle of the cross side wall of the ferroelectric capacitor to the plane on which the bottom electrode is formed is set to a value not reaching 75 degrees or more.
Referring to
FIG. 13
, there is shown a relationship between the taper angle of the cross side wall of the ferroelectric capacitor to the main surface of the substrate and short-circuit. It is assumed herein that a short-circuit has occurred when a leakage current density at an applied voltage of 3 V became 10
−5
A/cm
2
or higher. In the above-mentioned prior art, the etching is performed at nearly 90 degrees, so that, after etching of the platinum top electrode
45
, the platinum of the top electrode
45
redeposits to form a platinum-contained sidewall deposit
101
as shown in FIG.
10
A. After completion of dry-etching of the ferroelectric film
44
, a sidewall deposit
102
composed of elements constituting the ferroelectric film
44
remains along the platinum-contained sidewall deposit
101
as shown in FIG.
10
B. Although this sidewall deposit
102
is composed of the components of the ferroelectric film, the composition and crystal structure thereof are out of order, resulting in insufficient insulation. Referring to
FIG. 10C
, during etching of the platinum bottom electrode
43
, this deposit
102
composed of the components of the ferroelectric film is mostly removed. However, the platinum-contained sidewall deposit
101
still remains. Further, the platinum-contained sidewall deposit
103
may also be formed from the platinum bottom electrode. Thus, in the prior-art technology, depositing of platinum on the sidewall short-circuits the bottom and top electrodes
43
and
45
of the capacitor.
Referring to
FIG. 13
, it is clear that setting the angle of the cross sidewall of the platinum bottom electrode, the ferroelectric film and the top electrode to the main surface of the substrate to less than 75 degrees prevents the platinum deposits from being formed on the capacitor sidewall.
In
FIG. 13
, the angle of the cross sidewall of the platinum bottom electrode, the ferroelectric film, and the top electrode to the main surface of the substrate is shown; however, it is not always necessary to set the cross sectional sidewall of the entire capacitor to less than 75 degrees. For example, tilting the sidewall of only the ferroelectric film
44
relative to the main surface of the substrate by less than 75 degrees also provides an effect of preventing the platinum deposition from occurring. The effect can be made more conspicuous, however, by tilting together the sidewall of the platinum bottom electrode by less than 75 degrees.
It will be apparent that, instead of platinum, the top electrode
45
may be another rare metal such as iridium or ruthenium or a conductive oxide such as IrO
2
, RuO
2
, or ReO
3
. If platinum is not used for the top electrode
45
, the platinum-contained deposit is formed on the capacitor sidewall only when the platinum bottom electrode
43
is etched. As described above, tapering the capacitor side walls to the main surface of the substrate by less than 75 degrees prevents the short-circuit between the top electrode and the platinum bottom electrode.
The angle of the cross sidewall of the ferroelectric capacitor to the bottom surface of the bottom electrode is determined by the angle of the etching mask sidewall to the bottom surface of the bottom electrode. In the present invention, tungsten is used for the etching mask. When tungsten is etched by anisotropic dry etching, the angle of the tungsten sidewall to the bottom surface of the bottom electrode is determined by the angle of the photoresist side walls.
FIG. 11
shows a relationship between the sidewall taper angle of photoresist sidewall and resist baking temperature. Shown are test results obtained from two types of photoresists A and B. The results indicate that the sidewall taper angle gets larger as the baking temperature rises for both the photoresists. The photoresist A is composed of a material having a flat distribution over molecular weights of 100 to 30,000, while the photoresist B is composed of a material having a peak over molecular weights 2,000 to 3,000.
Fujisaki Yoshihisa
Kawakami Hiroshi
Kushida Keiko
Miki Hiroshi
Moniwa Masahiro
Antonelli Terry Stout & Kraus LLP
Dang Trung
Hitachi , Ltd.
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