Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

2000-08-31

2002-05-28

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C257S329000, C257S328000, C438S212000

Reexamination Certificate

active

06395604

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the invention
The present invention relates to a “semiconductor device with a trench, the inner wall of which is covered with a dielectric material and which intends to reduce the capacitance, and a method for fabricating the same.
2. Description of the Related Art
Conventionally, a trench is used as a gate of a vertical MOS transistor such as a power MOSFET.
The trench has two types of structures, i.e. a V (shape)-trench and a U (shape)-trench. For example, as for the former, JP-A-55-48968 mainly relates to a horizontal MOS transistor, but discloses, (refer to FIG. 14 of the JP-A-55-48968), a vertical MOS transistor including a source region(21) formed around a V-trench gate and a drain region(26) of N
−
type layer disposed at a bottom of the V-trench, namely discloses a V-trench MOS transistor. On the other hand, the latter is disclosed in detail in JP-A-7-326741 and JP-A-7-263692.
For example, in the vertical MOS transistor disclosed in JP-A-7-263692, as shown in
FIG. 12
of this application, an N
−
type semiconductor layer
10
is located on a N
+
type semiconductor substrate (not shown) and a P type semiconductor layer
11
is formed on the N
−
type semiconductor layer
10
. A trench
12
is formed from the surface of the semiconductor layer
11
so that the bottom and its vicinity is engaged in the N
−
type semiconductor layer
10
.
The inner wall of the trench
12
is covered with a gate insulating layer
13
. A conductive material such as polycrystalline silicon (poly-si)
14
is embedded in the trench
12
. An N
+
type source region
15
is formed around the trench
12
. A source electrode
17
is formed through the source region
15
and an insulating film
16
surrounded by the source region
15
and formed to expose the surface of the P
−
type semiconductor layer.
The surface of the semiconductor layer outside the trench
12
between the source region
15
and the drain region
10
is inverted from P type into N type to form a channel so that a current flows from the source region
15
toward the drain side.
In (FIG. 14 of) JP-A-48968, a “V-MOS”, having a trench of V-shape is shown. In the V-MOS”, an electric field is concentrated into the bottom so that breakage is likely to occur between the gate and drain. In addition, dry etching is difficult to carry out for machining and hence wet etching is commonly adopted. Therefore, the slanting angle of the V-trench is defined according to a crystal face so that the size of the opening cannot be increased. Further, owing to variations in the depth of the trench, C
gd
varies greatly. This leads to variations in the switching speed.
On the other hand, the “U-trench” of the MOS transistor disclosed in JP-A-7-263692 is machined by dry etching and draws “Round” shape on the bottom. Therefore, unlike the V-trench, an electric field is prevented from being concentrated at the bottom. The capacitance C
rss
=C
gd
between a trench bottom and N
−
type layer, however, is increased, thus retarding the switching speed.
Further, JP-A-7-326741 intends to remove a LOCOS to form a trench, (as shown in its FIG. 2). However, because the oxidizing step is required, the depth of the trench cannot be increased. In addition, owing to the formation of a bird's beak, defects are likely to occur below the bird's beak. When the LOCOS is grown to a deep position in order to increase the channel length, a long oxidizing time is required. Correspondingly, a bird's beak is further grown, and the size of the opening of the trench is increased, thus increasing the capacitance. Further, the cell density cannot be increased and reduction of the on-resistance is difficult.
The present invention intends to solve these problems, particularly to reduce the capacitance and to realize high speed switching while preventing reduction of the cell density.
Assuming that the switching time of the transistor is T, T∝&agr; (C
gs
+C
gd
). C
gs
represents a gate-source capacitance. Since the source electrode is in contact with the P
+
type semiconductor layer, it also represents the capacitance between the channel region and gate electrode. C
gd
represents a gate-drain capacitance.
SUMMARY OF THE INVENTION
The present invention intends to reduce the capacitance to improve the switching characteristic.
The present invention has been accomplished in view of the problem described above, and first, intends to solve the problem in such a manner that the inner wall of the trench extending from a bottom of the trench to the surface of the semiconductor layer has a slope, and an angle of a tangent line of the slope formed with the surface of the semiconductor layer decreases constantly from the vicinity of a lower end of the channel region toward the surface of the semiconductor layer.
As shown in
FIG. 11
, if angles of a tangent line of the slope for the surface of a semiconductor substrate, &agr;
1
, . . . &agr;n . . . are decreased toward the surface of the semiconductor substrate, the trench can have a sectional shape which is convex toward the inside of the trench. Further, the circumferential length of slope shaped trench as shown in
FIG. 14B
is small in comparison with that of the conventional rectangular type trench as shown in FIG.
14
A. Namely a slope can be formed to reduce the circumferential length of the trench. The structure of the trench according to the present invention is referred to as “&ggr; trench” in view of similarity of the shape.
A first aspect of the device is a semiconductor device of the present invention, which comprises:
a trench formed in a semiconductor layer of a first conduction type;
a gate oxide layer formed on an inner wall of said trench;
a gate conductor material embedded in said trench covered with the gate oxide layer; and
a channel region formed in a boundary of said semiconductor layer with said gate oxide layer,
wherein the inner wall of the trench extending from the bottom of said trench to the surface of the semiconductor layer has a slope, and an angle of a tangent line of said slope formed with the surface of said semiconductor layer decreases constantly from the vicinity of a lower end of said channel region toward the surface of said semiconductor layer.
As cell density is higher, although on-resistance is generally decreased, capacitance is increased. Contrary that, according to this device structure, capacitance can be decreased, even if the cell density is same as that of the conventional structure and thereby on-resistance remains the same as the conventional structure.
A second aspect of the device is a semiconductor device according to the first aspect, wherein said semiconductor layer is a first semiconductor layer of a first conduction type and said semiconductor device further comprises:
a source region formed on a surface of said first semiconductor layer;
a drain region of a second semiconductor layer of an opposite conduction type formed on a rear surface of said first semiconductor layer.
A third aspect of the method is a method of fabricating a semiconductor device and intends to solve the problem in such a manner of making etching with anisotropy stronger in a vertical direction with a deposit applied on a side wall to form the trench having a shape such that an angle of a tangent line of the slope formed with the surface of the semiconductor layer decreases constantly from the vicinity of a lower end of the channel region toward the surface of the semiconductor layer. This makes the etching speed in a vertical direction higher than in a horizontal direction, thereby completing the &ggr; trench. According to the method, adding to the effect according to the device above described, owing to the existence of the deposit applied on the side wall of the trench, without changing an opening width, capacitance can be reduced even in the conventional design scale as shown in FIG.
22
.
A fourth aspect of the method is a method of fabricating a semiconductor device, intends to solve

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