Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

1998-03-13

2001-07-10

Pham, Long (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S287000, C438S621000, C438S643000

Reexamination Certificate

active

06258647

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a semiconductor device, and more specifically, to a method of fabricating a semiconductor device having a dual gate.
2. Discussion of Related Art
The line pitch of semiconductor integrated circuits has been scaled down to a submicron level in order to improve operation characteristics and integration. This size reduction effectively reduces the space between adjacent gate lines used to form the semiconductor integrated circuit in a MOS transistor. Accordingly, a parasitic capacitance between the gate lines is increased, resulting in deterioration of the integrated circuit's signal transmission rate. The signal transmission rate depends on delay time which is determined by the resistance (R) of the gate line, and parasitic capacitance (C) between the gate lines.
For the purpose of increasing the signal transmission rate, the resistance in the gate line must be reduced or the parasitic capacitance must be decreased, e.g., by widening the space between the gate lines. Because extending the space between the gate lines has negative effects on circuit integration, a reduction of the resistance is preferred. For this reason, the gate has been conventionally formed of a polycide which results from depositing a silicide on a highly doped polysilicon layer.
As a CMOS transistor is highly integrated, the size of its NMOS and PMOS transistors is reduced, and their characteristics are deteriorated due to short channel effect and hot carrier effect. To solve this problem, the NMOS and PMOS transistors have been formed with a lightly doped drain (LDD) structure, and N-type impurities are highly doped into the gate of the NMOS and PMOS transistors. Thus, the channel of the PMOS transistor is formed in the bulk, not on the substrate. This produces punchthrough, decreasing the breakdown voltage.
Alternatively, a dual-gate CMOS transistor is proposed, in which the PMOS transistor has a highly doped P
+
-type gate, and the NOS transistor has a highly doped N
+
-type gate. With this structure, the channel of the PMOS transistor is formed on the surface of the substrate. Thus the breakdown voltage caused by the punchthrough is prevented from being decreased. The gate of the dual-gate CMOS transistor is also formed of the polycide consisting of a highly doped polysilicon and silicide. This prevents the signal transmission rate from being deteriorated in response to increased circuit integration.
However, in this structure, the impurity that is highly doped into the polysilicon is diffused into the silicide during high temperature process.
Furthermore, since impurity's diffusitivity in the silicide is higher than that in the polysilicon, the diffused impurity is laterally diffused in the silicide. Accordingly, the N-type and P-type impurities of the N
+
polysilicon and P
+
polysilicon are mutually diffused through the silicide, changing the threshold voltage of the MOS transistor. A technique for preventing the change of the threshold voltage is disclosed in U.S. Pat. No. 5,468,669, “Integrated circuit fabrication”, by Kuo-Hua Lee et. al.
FIGS. 1A
to
1
E show a conventional process of fabricating a semiconductor device. Referring to
FIG. 1A
, P-type and N-type impurities are sequentially doped into a substrate
11
, to form a P-well
13
and N-well
15
. A field oxide layer
17
, for electrically isolating single elements from each other, is formed where P-well
13
and N-well
15
come into contact with each other, through a local oxidation of silicon (LOCOS) process.
Referring to
FIG. 1B
, thermal oxidation is performed on the surface of P-well
13
and N-well
15
, forming a gate oxide layer
19
. Undoped polysilicon or amorphous silicon is deposited on field oxide layer
17
and gate oxide layer
19
through chemical vapor deposition (CVD), to form a silicon layer. N-type impurities such as As or P are ion-implanted in higher concentration into a portion of the silicon layer, corresponding to P-well
13
to form a N-type polysilicon layer
21
, and P-type impurities like B or BF
2
are ion-implanted in higher concentration into a portion of the silicon layer corresponding to N-well
15
to form a P-type polysilicon layer
22
. A refractory metal silicide layer
23
, such as tungsten silicide (WSix), is formed on N-type and P-type polysilicon layers
21
and
22
using CVD.
Referring to
FIG. 1C
, silicide layer
23
, and N-type and P-type polysilicon layers
21
and
22
are sequentially patterned through photolithography, to form a contact hole
25
exposing field oxide layer
17
. Contact hole
25
is formed at a position where N-type and P-type polysilicon layers
21
and
22
come into contact with each other. Referring to
FIG. 1D
, TiN is deposited on silicide layer
23
through CVD, to form a diffusion stop layer
27
.
FIG. 1D
shows a cross-section taken along line
1
D—
1
D of FIG.
1
C. As shown in the cross-section, a contact hole
25
is also formed in diffusion stop layer
27
above field oxide layer
17
.
Referring to
FIG. 1E
, diffusion stop layer
27
, silicide layer
23
, N-type and P-type polysilicon layers
21
and
22
, and gate oxide layer
19
are patterned, through photolithography, to expose portions of wells
13
and
15
, and field oxide layer
17
. N-type and P-type polysilicon layers
21
and
22
do not come into contact with each other, but they are electrically connected through diffusion stop layer
27
. That is, N-type and P-type polysilicon layers
21
and
22
are separated from each other, and diffusion stop layer
27
is formed therebetween using a mask aligned to contact hole
25
during the photolithography process. Thus, the impurities doped into the polysilicon layers
21
and
22
are prevented from being mutually diffused.
N-type and P-type polysilicon layers
21
and
22
, together with diffusion stop layer
27
and silicide layer
23
formed thereon, become gates
28
and
29
of NMOS and PMOS transistors. N-type impurities such as As or P, and P-type impurities like B or BF
2
are respectively ion-implanted in higher concentration into P-well
13
and N-well
15
, to thereby form impurities regions
31
and
33
. Since the N-type and P-type polysilicon layers
21
and
22
are separated from each other and the diffusion stop layer
27
is formed therebetween, the polysilicon layers
21
and
22
are electrically connected, but the impurities doped thereinto are not mutually diffused. Accordingly, it is possible to prevent the threshold voltage from being changed.
However, the above-described conventional method requires a first mask for isolating the N-type and P-type polysilicon layers from each other (FIG.
1
D), and a second mask for patterning them in order to form the gate (FIG.
1
E). Thus, it is difficult to align the gate patterning mask and the contact hole. Furthermore, the diffusion stop layer as well as the polysilicon layers should be etched when the gate is patterned. This complicates the process.
SUMMARY OF THE INVENTION
Accordingly, the present invention is directed to a method of fabricating a semiconductor device that substantially obviates one or more of the problems due to limitations and disadvantages of the related art.
An object of the present invention is to provide a method of fabricating a semiconductor device, which performs isolation of N-type and P-type polysilicon layers from each other and patterns them for the purpose of forming a gate, using one mask.
Another object of the present invention is to provide a method of fabricating a semiconductor device, which simplifies etching process during a gate patterning process, to thereby reduce the number of process step.
Additional features and advantages of the invention will be set forth in the description which follows, and in part will be apparent from the description, or may be learned by practice of the invention. The objectives and other advantages of the invention will be realized and attained by the structure particularl

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