Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2009-03-06
2010-12-14
Luu, Chuong A. (Department: 2892)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S257000, C438S586000, C438S584000
Reexamination Certificate
active
07851290
ABSTRACT:
A method of fabricating a semiconductor device, in which although a metal layer is included in a gate pattern, the gap-fill characteristic of contact plugs coupled to junctions can be improved and degradation in the data retention characteristic can also be prevented. According to the method, a semiconductor substrate in which lower gate patterns and gate hard mask patterns are sequentially stacked is first provided. Junctions are formed in the semiconductor substrate on both sides of each of the lower gate patterns. A first pre-metal dielectric layer is formed over the semiconductor substrate in which the hard mask patterns and the junctions are formed. Contact holes through which the junctions are exposed are formed in the first pre-metal dielectric layer. Gate trenches through which the lower gate patterns are exposed are formed by removing the hard mask patterns. Upper gate patterns, each including a metal layer, are formed in the gate trenches, and first contact plugs are formed in the contact holes.
REFERENCES:
patent: 7439157 (2008-10-01), Bian et al.
patent: 2009/0218639 (2009-09-01), Beyer et al.
patent: 10-2005-0010260 (2005-01-01), None
patent: 10-2008-0000900 (2008-01-01), None
Hynix / Semiconductor Inc.
Luu Chuong A.
Marshall & Gerstein & Borun LLP
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