Method of fabricating semiconductor device

Details Method of fabricating semiconductor device Method of fabricating semiconductor device

2001-09-18

2003-02-11

Sherry, Michael (Department: 2829)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S258000, C438S418000

Reexamination Certificate

active

06518124

ABSTRACT:

FIELD OF THE INVENTION
The present invention relates to a method of fabricating a semiconductor device including a logic circuit region and a memory region in which nonvolatile memory devices having two charge storage regions for one word gate are arranged in a matrix.
BACKGROUND OF THE INVENTION
As one type of nonvolatile semiconductor memory device, a MONOS (Metal Oxide Nitride Oxide Semiconductor) or SONOS (Silicon Oxide Nitride Oxide Silicon) memory device is known. In the MONOS or SONOS memory device, a gate insulating layer between a channel region and a control gate is formed of a laminate consisting of a silicon oxide layer and a silicon nitride layer, and charges are trapped in the silicon nitride layer.
A device shown in
FIG. 15
is known as such a MONOS nonvolatile semiconductor memory device (Y. Hayashi, et al., 2000
Symposium on VLSI Technology Digest of Technical Papers,
122-123).
In this MONOS memory cell
100
, a word gate
14
is formed on a semiconductor substrate
10
with a first gate insulating layer
12
interposed. A first control gate
20
and a second control gate
30
are disposed on either side of the word gate
14
in the shape of sidewalls. A second gate insulating layer
22
is present between the bottom of the first control gate
20
and the semiconductor substrate
10
. An insulating layer
24
is present between the side of the first control gate
20
and the word gate
14
. Another second gate insulating layer
22
is present between the bottom of the second control gate
30
and the semiconductor substrate
10
. Another insulating layer
24
is present between the side of the second control gate
30
and the word gate
14
. Impurity layers
16
and
18
forming a source region or a drain region are formed in the semiconductor substrate
10
in a region between the control gate
20
and the control gate
30
facing each other in the adjacent memory cells.
As described above, one memory cell
100
includes two MONOS memory elements, one on each side of the word gate
14
. These two MONOS memory elements can be controlled separately. Therefore, one memory cell
100
is capable of storing two bits of information.
BRIEF SUMMARY OF THE INVENTION
An objective of the present invention is to provide a method of fabricating a semiconductor device including MONOS nonvolatile memory devices each of which has two charge storage regions, in which a memory region including MONOS memory cells and a logic circuit region including a peripheral circuit for the memory and the like are formed on a single substrate.
According to the present invention, there is provided a method of fabricating a semiconductor device including: a memory region which has nonvolatile memory devices; and a logic circuit region which has a peripheral circuit for the nonvolatile memory devices. This method includes the following steps in this order:
a step of forming a first insulating layer over a semiconductor layer;
a step of forming a first conductive layer over the first insulating layer;
a step of forming a mask insulating layer over part of the first conductive layer disposed within the logic circuit region;
a step of forming a stopper layer over the first conductive layer and the mask insulating layer;
a step of etching part of the stopper layer, the mask insulating layer and the first conductive layer to form word gate layers in the memory region and to form gate electrodes of insulated-gate field-effect transistors in the logic circuit region;
a step of forming an ONO film over the entire surface of the memory region and the logic circuit region;
a step of forming a second conductive layer over the ONO film;
a step of anisotropically etching the second conductive layer to form control gates in the shape of sidewalls at least on both sides of each of the word gate layers in the memory region with the ONO film interposed;
a step of forming first impurity layers each of which forms a source region or a drain region of the nonvolatile memory devices, and forming second impurity layers each of which forms a source region or a drain region of the insulated-gate field-effect transistors;
a step of forming sidewall insulating layers at least on both sides of the gate electrodes;
a step of forming silicide layers on the surfaces of the first impurity layers and the second impurity layers;
a step of forming a second insulating layer over the entire surface of the memory region and the logic circuit region;
a step of polishing the second insulating layer to expose the stopper layer;
a step of removing the stopper layer; and a step of patterning the word gate layers in the memory region to form word gates of the nonvolatile memory devices in the memory region.


REFERENCES:
patent: 5408115 (1995-04-01), Chang
patent: 5422504 (1995-06-01), Chang et al.
patent: 5494838 (1996-02-01), Chang et al.
patent: 5969383 (1999-10-01), Chang et al.
patent: 6177318 (2001-01-01), Ogura et al.
patent: 6248633 (2001-06-01), Ogura et al.
patent: 6255166 (2001-07-01), Ogura et al.
patent: 6413821 (2001-09-01), Ebina et al.
Hayashi, Yutaka et al., “Twin MONOS Cell with Dual Control Gates”,2000 IEEE Symposium on VLSI Technology Digest of Technical Papers.
Chang, Kuo-Tung et al., “A New SONOS Memory Using Source-Side Injection for Programming”,1998 IEEE Electron Device Letters, vol. 19, No. 7, Jul. 1998, pp. 253-255.
Chen, Wei-Ming et al., “A Novel Flash Memory Device withSPlit Gate Source SideInjection an ONO Charge Storage Stack (SPIN)”,1997 Symposium on VLSI Technology Digest of Technical Papers, pp. 63-64.

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