Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-10-22
2001-04-10
Fourson, George (Department: 2823)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S253000, C438S304000, C438S307000, C438S596000
Reexamination Certificate
active
06214677
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a fabrication method for a dynamic random access memory (DRAM). More particularly, the present invention relates to a method of fabricating a self-aligned ultra short channel.
2. Description of Related Art
As the size of the semiconductor device has gradually been reduced according to the design rule, a photolithographic process usually adopted in the semiconductor process reaches a bottleneck in terms of controlling the critical dimension, since the process is limited by light resolution and depth of focus. Such problem has a serious impact on area reduction of a memory cell.
Conventionally, a more complicated mask, such as a phase shift mask (PSM) and special exposure technology, such as off-axis illumination (OAI) are used to pattern a photoresist, so that the light resolution is improved. Although the critical dimension has been reduced as a consequence of the combination described above, the production cost of the integrated circuit has been greatly increased.
With advanced technology, the channel length of the MOS device is reduced during semiconductor process to significantly improve the operation speed of a transistor. However, problems such as short channel effects and associated hot electron effects occur when channel length is reduced to a certain extent, and consequently lead to an electrical breakdown. One solution to improve the short channel effects involves forming a doped region that has a lower doped concentration than that of a source/drain region, with the doped region known as a lightly doped drain (LDD) region.
In addition, the size of the memory cell and an area occupied by the DRAM capacitor have also been reduced, respectively, with respect to an increase in DRAM integration. Such size reduction for the memory cell can cause a decrease in a capacitance. In order to maintain the capacitance in an acceptable range, the high integration DRAM adopts a three-dimensional capacitor structure, such as a stacked capacitor, a trench stacked capacitor, and a crown shape capacitor to provide a large capacitor area. However, the increased complexity of the capacitor structure has caused an increase in the height of the capacitor and an increased capacitance in turns. Thus, a storage node consisting of a capacitor-over-bit line (COB) layout is developed, wherein the layout is not limited in terms of space for the capacitor.
SUMMARY OF THE INVENTION
The invention provides a method for fabricating a self-aligned ultra short channel with double spacers, which serve as a hard mask to form a DRAM having an ultra short channel in a self-aligned process. In the invention, the channel length is reduced, while the doping in the node opening side of the lightly doped region and the bit line side of the lightly doped region can be adjusted to optimize the device property.
As embodied and broadly described herein, the invention provides a fabrication method for a self-aligned ultra short channel. The method first provides a substrate with isolation structures formed therein. A pad oxide layer and a mask layer are then formed in sequence on the substrate, and patterned to form an opening which exposes the substrate. An ion implantation step is performed to form a first lightly doped region in the substrate, while a first spacer is formed on the sidewall of the opening. With the first spacer serving as a hard mask, another ion implantation step is performed, so that a first heavily doped region is formed in the substrate. The first lightly doped region and the first heavily doped region constitute a source region, while a first lightly doped drain (LDD) region is formed at a location where the first lightly doped region does not overlap with the first heavily doped region. A conducting layer that covers the mask layer and fills the opening is formed, followed by planarizing the conducting layer for forming a bit line, while the mask layer and the pad oxide layer are subsequently removed to expose the substrate. A gate oxide layer is formed on the exposed substrate, while a second spacer is formed to cover a sidewall of the first spacer and a part of the gate oxide layer. With the second spacer serving as a hard mask, an ion implantation step is performed to form a second lightly doped region. An oxide layer is formed to cover the gate oxide layer before planarizing the oxide layer, the first spacer, the second spacer, and the conducting layer. A patterned dielectric layer is formed to cover the planarized oxide layer, the first spacer, the second spacer, and the conducting layer with formation of a contact opening which exposes the conducting layer before filling the contact opening with a patterned conducting layer. Furthermore, an inter polysilicon dielectric (IPD) layer is formed on the dielectric layer, followed by patterning the IPD layer, the dielectric layer, the oxide layer, and the gate oxide layer, whereby a storage node opening which exposes the second lightly doped region is formed. Another ion implantation step is performed to form a second heavily doped region in the substrate. The second lightly doped region and the second heavily doped region constitute a drain region, and a second LDD region is formed at a location where the second lightly doped region does not overlap with the second heavily doped region. A conducting layer which covers the inter polysilicon dielectric layer and fills the storage node opening is formed and patterned to complete formation of a storage electrode of a capacitor.
Accordingly, the second spacer is made of tungsten, whose fabrication technology is mature, so it is possible to fabricate tungsten spacer with a thickness smaller than about 0.1 &mgr;m. Therefore, in the invention, the MOS DRAM device having an ultra short channel can be fabricated with the tungsten spacer serving as a hard mask, and a lower photolithographic requirement, both of which result in a reduction of the channel length. Hence, this increases the operation speed of the device.
It is to be understood that both the foregoing general description and the following detailed description are exemplary, and are intended to provide further explanation of the invention as claimed.
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Estrada Michelle
Fourson George
Thomas Kayden Horstemeyer & Risley
United Microelectronics Corp.
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