Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1998-07-28
2001-03-13
Booth, Richard (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
Reexamination Certificate
active
06200856
ABSTRACT:
BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a stacked gate “flash” electrically-erasable programmable read only memory (“Flash EEPROM”) cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as CMOS, microcontrollers, microprocessors, application specific integrated circuits, embedded memory applications, among others.
Industry has used or proposed a variety of memory devices. An example of such a memory device is an erasable programmable read-only memory (“EPROM”) device. The EPROM device is both readable, writable, and erasable, i.e., programmable. The EPROM is implemented using a floating gate field effect transistor, which has certain binary states. That is, a binary state is represented by the presence or absence of charge on the floating gate. The charge is generally sufficient to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
A wide variety of EPROMs is available. In a traditional form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are commonly referred to as ultraviolet erasable programmable read-only memories (“UVEPROM”s). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory (“EEPROM” or “E
2
PROM”). EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling. Still another form of EPROM is a “Flash EPROM,” which is programmed using hot electrons and erased using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be erased in a “flash” or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler-Nordheim tunneling, and are commonly called “Flash cells” or “Flash devices.”
Flash memory cells, however, are often bulky and difficult to fabricate in a desired space due to complex geometries of the multiple gate layers used to form the control and floating gates. Accordingly, flash memory cells generally cannot be integrated as tightly or closely as other types of memory devices. Additionally, flash memory cells often require a high gate coupling ratio to achieve desirable programmability and functionality. High gate coupling ratios are often achieved by way of increasing the surface area of the control gate relative to the floating gate while reducing the surface area of the floating gate that is coupled to the channel region of the memory cell. Unfortunately, it is often difficult to increase the gate coupling ratio without significantly increasing the size of the memory cell.
From the above it is seen that a flash memory cell structure that is relatively easy to fabricate, cost effective, and reliable is clearly desired.
SUMMARY OF THE INVENTION
According to the present invention, a technique including a method and device for the fabrication of an integrated circuit device such as a flash memory is provided. In an exemplary embodiment, the present invention provides a self-aligned stacked gate flash memory device using a novel sequence of fabrication processes. This self-aligned gate reduces the size of the resulting flash memory cell according to certain embodiments.
In a specific embodiment, the present invention provides a method of forming a semiconductor integrated circuit device that has a self-aligned gate structure. The method includes a variety of steps such as forming a plurality of isolation regions in a substrate, which is commonly a silicon wafer. Each of the plurality of isolation regions is defined by a volume of isolation material (e.g., CVD oxide) that is defined in the substrate, and that is defined extending outside the substrate to form a recessed region (e.g., trench) between at least two of the isolation regions. The method also includes a step of forming a thickness of material (e.g., polysilicon) in the recessed region and overlying the isolation regions, where the thickness of material can be defined by a substantially continuous layer overlying and filling the recessed region and overlying the isolation regions. A step of planarizing the thickness of material occurs by removing a portion of the thickness of material overlying the isolation regions to expose an upper surface of the isolation regions to form a substantially planar surface from the thickness of material overlying the recessed region and the isolation regions. The planarizing step forms, for example, a self-aligned floating gate structure from the thickness of material. A control gate is formed over the floating gate to form, for example, a stacked gate structure.
In an alternative specific embodiment, the present invention provides a novel memory integrated circuit, such as a flash memory device, but can be others. The device includes a semiconductor substrate. A first trench isolation region and a second trench isolation region are defined in the semiconductor substrate. The trench isolation regions has an active region defined in a recessed region between the first trench isolation region and the second trench isolation region. A tunnel dielectric layer is defined overlying the active region. The device also includes a self-aligned floating gate layer defined within the recessed region of the active region. To complete the gate structure, a dielectric layer is defined overlying the floating gate layer, and a control gate layer is defined overlying a portion of the floating gate layer to form, for example, a stacked gate structure. The present self-aligned gate structure reduces cell size and improves device integration, as well as other features.
Numerous benefits are achieved using the present invention over preexisting or conventional techniques. In some embodiments, the present invention can provide a smaller cell size that improves device integration using a self-aligned poly-1 process. Additionally, the present invention can use presently available fabrication tools, such as chemical mechanical polishing or planarization, which do not require substantial capital costs if these tools are already available. Furthermore, the invention can prevent misalignment errors in some embodiments using the present self-aligned process. Moreover, gate coupling ratio can also be increased by way of the present self-aligned poly-1 process. These and other benefits are described throughout the present specification and more particularly below.
The present invention achieves these benefits in the context of known process technology. However, a further understanding of the nature and advantages of the present invention may be realized by reference to the latter portions of the specification and attached drawings.
REFERENCES:
patent: 5180680 (1993-01-01), Yang
patent: 5488586 (1996-01-01), Madurawe et al.
patent: 5595924 (1997-01-01), Yuan et al.
patent: 5767005 (1998-06-01), Doan et al.
patent: 6008112 (1999-12-01), Acocella et al.
Booth Richard
Townsend and Townsend / and Crew LLP
Winbond Electronics Corporation
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