Method of fabricating self-aligned split gate flash memory cell

Details Method of fabricating self-aligned split gate flash memory cell Method of fabricating self-aligned split gate flash memory cell

1998-07-28

2001-01-09

Chaudhari, Chandra (Department: 2813)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S596000

Reexamination Certificate

active

06171908

ABSTRACT:

BACKGROUND OF THE INVENTION
The present invention relates to semiconductor integrated circuits and their manufacture. The invention is illustrated in an example with regard to the manufacture of a “flash” electrically-erasable programmable read only memory (“Flash EEPROM”) cell, but it will be recognized that the invention has a wider range of applicability. Merely by way of example, the invention may be applied in the manufacture of other semiconductor devices such as CMOS, microcontrollers, microprocessors, application specific integrated circuits, embedded memory applications, among others.
Industry has used or proposed a variety of memory devices. An example of such a memory device is an erasable programmable read-only memory (“EPROM”) device. The EPROM device is both readable, writable, and erasable, i.e., programmable. The EPROM is implemented using a floating gate field effect transistor, which has certain binary states. That is, a binary state is represented by the presence or absence of charge on the floating gate. The charge is generally sufficient to prevent conduction even when a normal high signal is applied to the gate of the EPROM transistor.
A wide variety of EPROMs is available. In a traditional form, EPROMs are programmed electrically and erased by exposure to ultraviolet light. These EPROMs are commonly referred to as ultraviolet erasable programmable read-only memories (“UVEPROM”s). UVEPROMs can be programmed by running a high current between a drain and a source of the UVEPROM transistor while applying a positive potential to the gate. The positive potential on the gate attracts energetic (i.e., hot) electrons from the drain-to-source current, where the electrons jump or inject into the floating gate and become trapped on the floating gate.
Another form of EPROM is the electrically erasable programmable read-only memory (“EEPROM” or “E
2
PROM”). EEPROMs are often programmed and erased electrically by way of a phenomenon known as Fowler-Nordheim tunneling. Still another form of EPROM is a “Flash EPROM,” which is programmed using hot electrons and erased using the Fowler-Nordheim tunneling phenomenon. Flash EPROMs can be erased in a “flash” or bulk mode in which all cells in an array or a portion of an array can be erased simultaneously using Fowler-Nordheim tunneling, and are commonly called “Flash cells” or “Flash devices.”
Flash memory cells, however, are often bulky and difficult to fabricate in a desired space due to complex geometries of the multiple gate layers used to form the control and floating gates. Accordingly, flash memory cells generally cannot be integrated as tightly or closely as other types of memory devices. Additionally, flash memory cells often require a high gate coupling ratio to achieve desirable programmability and functionality. High gate coupling ratios are often achieved by way of increasing the surface area of the control gate relative to the floating gate while reducing the surface area of the floating gate that is coupled to the channel region of the memory cell. Unfortunately, it is often difficult to increase the gate coupling ratio without significantly increasing the size of the memory cell.
From the above it is seen that a flash memory cell structure that is relatively easy to fabricate, cost effective, and reliable is clearly desired.
SUMMARY OF THE INVENTION
According to the present invention, a technique including a method and device for the fabrication of an integrated circuit such as a flash memory cell is provided. In an exemplary embodiment, the present invention provides a self-aligned floating gate layer or poly-1 layer using a novel sequence of fabrication processes. This self-aligned floating gate layer reduces the size of the resulting flash memory cell according to certain embodiments.
In a specific embodiment, the present invention provides a novel method of forming a semiconductor integrated circuit device, such as flash memory devices. The method includes a variety of steps such as providing a semiconductor substrate, which is commonly a silicon wafer. Field isolation regions including a first isolation region and a second isolation region are defined in the semiconductor substrate. An active region is defined between the first and second isolation regions, and is generally defied in a recessed region between the first isolation region and the second isolation region. The isolation regions are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. The method also includes a step of forming a dielectric layer overlying the active region, where the dielectric layer can be a tunnel oxide layer for a flash memory device.
A thickness of material such as polysilicon is deposited overlying the first isolation region, the second isolation region, and the active region. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step. In a preferred embodiment, the step of selectively removing is performed using chemical mechanical polishing or planarization. The self-aligned material region can be a floating gate in, for example, the flash memory device.
In an alternative embodiment, the present invention provides a memory cell with a self-aligned floating gate structure. The memory cell includes a semiconductor substrate that has a first isolation region, and a second isolation region defined in the semiconductor substrate. Between the isolation regions is a recessed region where an active region is defined in the recessed region between the first isolation region and the second isolation region. A tunnel dielectric layer (e.g., oxide, oxynitride, nitride) is defined overlying the active region. A self-aligned floating gate layer is defined within the recessed region of the active region. A dielectric layer is defined overlying the floating gate layer. A control gate layer is defined overlying a portion of the floating gate layer. The floating gate layer and the control gate layer define a split gate structure. The self-aligned floating gate layer reduces cell size and is generally easier to fabricate accurately than conventional techniques.
In still a further embodiment, the present invention provides a method of forming an integrated circuit device having a self-aligned gate layer or conductive layer. The method includes a variety of steps such as providing a substrate, which is commonly a silicon wafer. Field isolation regions including a first isolation region and a second isolation region are defined in the semiconductor substrate. A recessed region is defined between the first and second isolation regions during the formation of the isolation regions. The isolation regions are made using a local oxidation of silicon process, which is commonly called LOCOS, but can be others. A thickness of material such as polysilicon is deposited overlying or on the first isolation region, the second isolation region, and the active region. The thickness of material fills the recessed region and protrudes outside the recessed region as it lays over the isolation regions, which are commonly higher than the recessed region relative to the isolation regions. A step of selectively removing portions of the thickness of material overlying portions of the first isolation region and the second isolation region is performed, where the removing step forms a substantially planar material region in the recessed region. The substantially planar material region is self-aligned into the recessed region using the removing step.
Numerous benefits are achieved using the present invention over pre-existing or conventional techniques. In some embodiments, the present invention can provide a smaller cell size that improves device integration using a self-aligned poly-1 process. Additionally, the present i

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