Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2003-02-07
2004-07-20
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S624000, C438S631000
Reexamination Certificate
active
06764907
ABSTRACT:
FIELD OF THE INVENTION
The present invention generally relates to silicon carbide (SiC) semi-conductor devices, and in particular, to methods of forming self-aligned SiC devices.
BACKGROUND OF THE INVENTION
Silicon carbide is a semiconductor material with desirable material properties for constructing power devices. These material properties include among other things, a wide bandgap, a high thermal conductivity, high breakdown field strength, and a high electron saturation velocity. One example of such a power device is a bipolar junction transistor (BJT). BJT's are well-known and frequently used semiconductor devices that are generally defined by two back-to-back p-n junctions formed in a semiconductor material in close proximity. In operation, current enters a region of the semiconductor material adjacent one of the p-n junctions called the emitter. Current exits the device from a region of the material adjacent the other p-n junction called the collector. The collector and emitter have the same conductivity type and include a thin layer of semiconductor material having the opposite conductivity positioned between them, referred to as the base.
One of the requirements for an operable and useful BJT device is an appropriate semiconductor material from which it can be formed. The most commonly used material is silicon (Si), with recent attention being paid to materials such as gallium arsenide (GaAs) and indium phosphide (InP). While the potential of SiC is recognized, appropriate techniques for producing devices is lacking, because the requirements of specific devices, such as devices utilized in radio frequency (RF) applications, are often difficult to achieve using SiC. For instance, performance optimization in a device, such as a BJT for an RF power amplifier, requires minimizing base resistance, maximizing power densities, and minimizing parasitics. To accomplish these characteristics, the geometry and spacing of the base and the emitter, as well their respective contacts must be carefully controlled. Furthermore, such devices require careful control of the conductivity and thickness of the emitter, base, and collector layers, as well as the parasitic base-collector capacitance to achieve desired oscillation frequencies and power gains. In the case of a device, such as a BJT made from SiC, the high base sheet resistance and difficulty in making low-resistivity ohmic contacts, (due to the large mismatch between the valence band energy of SiC and the work function of common metals), makes such devices difficult to produce.
To achieve the above-described geometries and spacing in a SiC device, it is desirable to construct the device in a self-aligned manner. Self-alignment in this context means that the relative spacing of features of the device, such as contacts, is automatically controlled by the processing sequence and process parameters, rather than by the careful alignment prior to exposure of a photo sensitive layer. Unfortunately, self-alignment is problematic in SiC devices due to the high processing temperatures typically involved. For example, ion implantation of a highly-doped contact region to form a self-aligned contact layer is the commonly utilized approach in the semiconductor, industry to achieve self-alignment. This approach typically utilizes an implant mask to define the ion implanted regions of the device. However, when this technique is applied to SiC devices, the subsequent anneal process required to restore the crystal structure after implantation must be performed at very high temperatures (generally 1400-1800° C.). Such high temperatures require that the masking material utilized for the implantation be removed during the anneal process such that the implant mask can no longer-be used to self-align other features of the device.
SUMMARY OF THE INVENTION
In view of the foregoing, a primary object of the present invention is to provide improved methods of forming SiC devices. Another object of the present invention is to provide improved methods of forming self-aligned SiC devices. Another object of the present invention is to provide improved methods of forming self-aligned contacts on SiC devices. Another object of the present invention is to improve SiC device performance. A related object of the present invention is to provide improved SiC devices configured for operation in applications including without limitation, RF power transistors. Another object of the present invention is to increase power densities, optimize doping densities, and minimize parasitics in SiC devices.
One or more of the above objectives and additional advantages may be realized by a first aspect of the present invention, which provides a method of forming a self-aligned SiC device. The method includes the steps of providing a multi-layer laminate including at least a first and second layer of SiC material, defining at least one mesa structure in one of the first and second layers, and utilizing the mesa structure and at least one planarization step to construct the device in a self-aligned manner. According to this method, SiC devices including without limitation a junction, a transistor, a diode, thyristor, etc. may be formed in a self-aligned manner.
Various refinements exist of the features noted in relation to the subject first aspect of the present invention. Further features may also be incorporated in the subject first aspect as well. These refinements and additional features may exist individually or in any combination. For instance, the defining step may include the steps of forming a first and second mask on the one of the first and second layers and etching the mesa structure using the second mask. Subsequent to removal of the second mask, the method may include the step of ion implanting a first portion of the multi-layer laminate to produce a first doped portion using the first mask. In this regard, the method may further include the step of forming sidewalls on the emitter mesa prior to the ion implantation and using the sidewalls and the first mask to define the first doped portion.
According to another feature, the present method may further include the steps of forming second sidewalls on the first sidewalls and ion implanting a second portion of the multi-layer laminate using the second sidewalls to define a second doped portion. In one example, of a BJT device produced according to the present method, the second doped portion includes a higher doping density than the first doped portion to reduce the base-collector capacitance.
According to a first embodiment of the present method, the mask material is removed prior to annealing the device. In this regard, subsequent to removal of the mask material, the method includes the step of annealing the multi-layer laminate to restore the crystal structure. According to a second embodiment of the present method, the mask material comprises a material, e.g. carbon, diamond, tungsten etc., capable of withstanding the high temperatures, e.g. generally 1400-1800° C., of the anneal process. In this case, the mask material is not removed prior to the annealing step, and may be utilized subsequent to the annealing step, to construct the device in the self-aligned manner.
According to another feature, the present method may further include the steps of forming sidewalls on the mesa structure and conformally depositing a contact metal layer on the multi-layer laminate. The contact metal layer may then be formed into self-aligned contact areas using planarization. In this regard, the method may further include the steps of conformally depositing a planarization layer on the contact metal layer and removing a portion of the planarization layer to expose a portion of the first contact metal layer. The exposed contact metal may then be removed to form contact areas in the non-removed portions of the device, followed by removal of the remaining planarization layer.
According to another feature, the present method may further include the steps of conformally depositing another planarization layer on the multi-layer laminat
Torvik John T.
Van Zeghbroeck Bart J.
Lindsay Jr. Walter L.
Marsh & Fischmann & Breyfogle LLP
Niebling John F.
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