Method of fabricating self-aligned contacts and local interconne

Details Method of fabricating self-aligned contacts and local interconne Method of fabricating self-aligned contacts and local interconne

1996-10-16

1998-06-02

Chaudhari, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438633, 438664, H01L 218249

Patent

active

057598827

ABSTRACT:
A method of fabricating external contacts in an integrated circuit structure utilizes chemical mechanical polishing (CMP). The structure includes an active device substrate region defined by field oxides. First and second diffusions formed in the active region define a substrate surface region therebetween. In accordance with the method, a layer of amorphous or polycrystalline silicon is formed in contact with the diffusion regions, subjected to a chemical mechanical polishing (CMP) step and then etched to form external contacts. The process flow can be applied to CMOS technologies and adapted to bipolar technologies to provide a BiCMOS flow.

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C.T. Liu et al., "MOSFET's with One-Mask Sealed Diffusion-Junctions for ULSI Applications", IEEE Electron Device Letters, vol. 16 No. 8, pp. 363-365 Aug. 1995.
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T.M. Li et al., "The Control of Polysilicon/Silicon Interface Processed by Rapid Thermal Anneal", IEEE Bipolar Circuits and Technology Meeting May 1991.
Tzu-Yin Chiu et al., "Non-overlapping Super Self-Aligned BiCMOS with 87ps Low Power ECL", IEEE pp. 752-755 Aug. 1988.

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