Method of fabricating self-aligned contact in embedded DRAM

Details Method of fabricating self-aligned contact in embedded DRAM Method of fabricating self-aligned contact in embedded DRAM

1998-12-08

2001-03-13

Elms, Richard (Department: 2824)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S270000, C438S706000, 43, 43, 43, 43, 43

Reexamination Certificate

active

06200848

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of Invention
The present invention relates to a method of fabricating a self-aligned contact (SAC). More particularly, the present invention relates to a method of fabricating a contact in an embedded dynamic random access memory (DRAM).
2. Description of Related Art
FIGS. 1A through 1B
are schematic, cross-sectional views showing a conventional method of fabricating a self-aligned contact in an embedded DRAM. Referring to
FIG. 1A
, a semiconductor substrate
104
is provided. A shallow trench isolation (STI) structure
106
is formed on the substrate
104
to define a memory region
100
and a logic region
102
in an embedded dynamic random access memory (DRAM). The memory region
100
has an N-type metal oxide semiconductor (MOS)
108
and an N-type source/drain region
110
formed therein. The logic region
102
has an N/P-type MOS
112
having a dual gate structure and an N-type source/drain region
114
formed therein. A dielectric layer
116
is formed on the substrate
100
to cover the NMOS
108
and the N/PMOS
112
. The dielectric layer
116
is patterned to form a contact hole in the memory region
100
. The contact hole is filled with a conductive layer
118
, which is composed of a polysilicon layer with doped N-type ions and a tungsten silicide layer. A portion of the conductive layer
118
extends to surface of the dielectric layer
116
neighboring the contact hole. Thus, the conductive layer
118
can be electrically coupled to the source/drain region
110
.
Referring to
FIG. 1B
, an inter-layer electric (ILD) layer
120
is deposited over the substrate
104
. Then, a planarization process is performed. Via holes are respectively formed in the memory region
100
and in the logic region
102
by photolithography and etching methods. The via holes are filled with a tungsten layer to respectively form vias
122
a
,
122
b
in the memory region
100
and in the logic region
102
. Thus, the vias
122
a
,
122
b
can be electrically coupled to the conductive layer
118
in the contact hole and the source/drain regions
110
.
While etching the inter-layer electric layer
120
to form the via
122
a
in the memory region
100
and the via
122
b
in the logic region
102
, the tungsten layer of the conductive layer
118
and the silicon substrate
104
are respectively used as the etching stops. Due to the different etching stops and much different etching depths, alignment is difficult in the etching process, even when the etching stops are over-etched. The via
122
b
in the logic region
102
has larger aspect ratio because of the much deeper via
122
b
. Therefore, it is more difficult to align in the etching process.
In order to improve the alignment process mentioned above, a contact filled with a conductive layer of N-type doped polysilicon/tungsten silicide can be formed in the logic region
102
during alignment contact formation in the dielectric layer
116
in the memory region
100
. The conductive layer in the logic region
102
is electrically coupled to the source/drain region
114
. However, the MOS
112
in the logic region
102
has an N/P type dual gate structure, and a junction will be appear between the PMOS source/drain region
114
and the N-type conductive layer in the logic region
102
. This is not the required electric connection. Therefore, the method is not used to solve the problem of the different depths while etching.
In addition, a method of forming a borderless contact is also used to overcome the difficulties of the different etching depths in the memory region and in the logic region due to the gradually reduced dimension of semiconductors. But it still has many problems, as shown as FIG.
2
.
FIG. 2
is a schematic, cross-sectional view showing a borderless contact. The distance between a MOS
202
and a STI structure
204
are much smaller to fit the design rule. A borderless contact
208
is formed in a dielectric layer
206
. In order to reduce dimensions of devices, a portion of the borderless contact
208
is formed above the STI structure
204
. Since the material of both the dielectric layer
206
and the STI structure
204
is oxide, it is difficult to stop on the substrate
200
while etching the dielectric layer
206
to form a contact hole
208
, so that the substrate
200
is over-etched. An undesired trench
210
is formed in the substrate
200
. Current leakage will occur while filling with a conductive layer in the later process.
FIG. 3
is a schematic, cross-sectional view showing a borderless contact. An oxide layer
304
and a silicon nitride layer
306
are sequentially formed over a MOS structure
302
on a substrate
300
. A planarized dielectric layer
308
is formed over the substrate
300
. A borderless contact hole
310
will be formed by photolithography and etching methods. While etching the dielectric layer
308
, the silicon nitride layer
306
is first used as an etching stop. Then, the etched thickness of the oxide layer
304
is accurately controlled while etching the oxide layer
304
. A source/drain region
312
beside the MOS
302
is completely exposed. Thus, a conductive layer formed subsequently can be easily coupled to a source/drain region
312
beside the MOS
302
. However, the required etched depth of the contact hole
310
in the embedded DRAM is about 22000 Å. Since the dielectric layer
308
is much thicker than the silicon nitride layer
306
, the silicon nitride layer
306
is over-etched during the forming step of the contact hole
310
. It causes the process in which the silicon nitride layer
306
is used as an etching stop to fail. If thickness of the silicon nitride layer
306
is increased, problems of stress will develop. Therefore, the borderless contact cannot achieve its efficacy in the above-mentioned conditions.
SUMMARY OF THE INVENTION
Accordingly, the present invention is to provide a method for overcoming difficulties of forming and aligning a contact hole, because thickness of dielectric layers in a memory region and in a logic region are much different.
Another purpose of the invention is to provide a method for improving current leakage caused by over-etching a contact hole while forming a borderless contact hole.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a self-aligned contact (SAC). A substrate is defined as a memory region and a logic region. MOS structures and source/drain regions are respectively formed in the memory region and in the logic region. A patterned dielectric layer is formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region to expose the source/drain regions. The contact hole is filled with a silicide layer. A portion of the silicide layer extends to the surface of the dielectric layer neighboring the contact hole. A defined inter-layer dielectric layer is formed over the substrate. Then, vias are respectively formed in the memory region and in the logic region. The vias are filled with conductive layers. Thus, a self-aligned contact is formed.
To achieve these and other advantages and in accordance with the purpose of the invention, as embodied and broadly described herein, the invention provides a method of fabricating a self-aligned contact. A substrate is defined as a memory region and a logic region. MOS structures and source/drain regions are respectively formed in the memory region and in the logic region. An oxide layer, a hard material layer and a defined dielectric layer are sequentially formed over the substrate. Contact holes are respectively formed in the memory region and in the logic region to expose the hard material layer. The hard material layer exposed by the contact holes is removed to expose the oxide layer. Then, the exposed oxide layer is removed to expose the source/drain region. The contact hole is filled with a silicide layer. A portion of the silicide layer extends to surface of the die

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