Method of fabricating quantum well structure

Semiconductor device manufacturing: process – Making device or circuit emissive of nonelectrical signal – Compound semiconductor

Reexamination Certificate

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C438S022000, C438S025000, C438S035000, C438S047000, C257S014000, C257S015000, C257S018000, C257S020000, C257S024000, C257SE21108

Reexamination Certificate

active

07955881

ABSTRACT:
In the method of fabricating a quantum well structure which includes a well layer and a barrier layer, the well layer is grown at a first temperature on a sapphire substrate. The well layer comprises a group III nitride semiconductor which contains indium as a constituent. An intermediate layer is grown on the InGaN well layer while monotonically increasing the sapphire substrate temperature from the first temperature. The group III nitride semiconductor of the intermediate layer has a band gap energy larger than the band gap energy of the InGaN well layer, and a thickness of the intermediate layer is greater than 1 nm and less than 3 nm in thickness. The barrier layer is grown on the intermediate layer at a second temperature higher than the first temperature. The barrier layer comprising a group III nitride semiconductor and the group III nitride semiconductor of the barrier layer has a band gap energy larger than the band gap energy of the well layer.

REFERENCES:
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patent: 2005/0199903 (2005-09-01), Kyono et al.
patent: 2006/0268953 (2006-11-01), Ikedo et al.
patent: 2007/0012932 (2007-01-01), Kobayakawa et al.
patent: 2002-043618 (2002-02-01), None
patent: 2006-210692 (2006-08-01), None
patent: 2006-237281 (2006-09-01), None
patent: 2006-332258 (2006-12-01), None
patent: 2008-118049 (2008-05-01), None

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