Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
1999-09-28
2001-09-18
Bowers, Charles (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S197000, C438S237000, C438S238000
Reexamination Certificate
active
06291281
ABSTRACT:
BACKGROUND OF THE INVENTION
1. Field of the Invention
The invention relates in general to a method of fabricating a protection structure. More particularly, the invention relates to a method of fabricating a protection structure which can be used to protect both a PMOS and an NMOS.
2. Description of the Related Art
In an integrated circuit, after the formation of certain devices, there are still some processes to be performed to complete the circuit layout. For example, after a PMOS or an NMOS is formed on a substrate, to obtain an electrical connection between PMOS or NMOS and other devices or terminals, a conductive layer is formed and patterned. While patterning the conductive layer, an etching step is inevitable. The plasma or other charged particles used to etch the conductive layer very often damage the NMOS or PMOS formed on the substrate. To protect the PMOS or NMOS from being damaged by the accumulated charged particles or carriers, a protection diode (PD) is formed in prior fabrication technology. Typically, for an NMOS, an N+/P− diode is formed to direct negative charges to the ground. In contrast, for a PMOS, a P+/N− diode is formed to dissipate the positive charges.
FIG.
1
A and
FIG. 1B
respectively show circuit diagrams of protection diodes used for NMOS and PMOS. As shown in the figures, since the polarity of protection diodes required by the NMOS and the PMOS are different, if one is to fabricate a single protection diode in one substrate having both PMOS and NMOS, the conventional technique cannot achieve the objective.
Furthermore, after the formation of the devices in and on the substrate, a multi-level interconnect is typically formed on the devices to complete the circuit layout. The electrical connection between the gate and the protection diode very often degrades the performance and electrical characteristics of the circuit.
SUMMARY OF THE INVENTION
The invention provides a method of fabricating a protection structure. The protection structure comprises a contact resistor, or a combination of a contact resistor and a protection diode. The protection structure can protect both an NMOS and a PMOS from plasma damage without interchanging the polarity thereof. Furthermore, in the invention, after a top metal layer of an interconnect of the integrated circuit is formed and patterned, the electrical connection between the gate of the devices such as an NMOS or a PMOS and the protection structure is open, so that the circuit performance is enhanced. Therefore, in an early stage of the fabrication process, the devices, including the NMOS, PMOS, or even gate oxides of the devices can be protected from plasma damage by connecting the gate with the protection structure. While the circuit layout is complete, the connection between the gate and the protection structure is open to obtain an improved performance of the circuit.
In the fabricating method of the invention, a substrate of a first conductive type is provided. The substrate comprises at least a gate oxide layer thereon, and a gate formed on the gate oxide layer. A first heavily doped region of a first conductive type and a second heavily doped region of a second conductive type are formed in the substrate without any physically mutual connection. Or alternatively, only one heavily doped region of the first conductive type is formed. An inter-layer dielectric layer (ILD) is formed on the substrate to cover the first and second heavily doped regions, the gate and the substrate. Plugs are formed to penetrate through the dielectric layer to couple the gate, the first and the second heavily doped regions. A first metal layer is formed on the inter-layer dielectric layer to couple with the contact resistor, the protection diode and the gate. A first inter-metal dielectric layer is formed on the metal layer. The first inter-metal dielectric layer is etched to form first via holes or contact window openings. Among the first openings, there is one opening exposing the first metal layer. A glue layer is formed on the inter-metal dielectric layer and on a surface of the openings. It is to be noted that for those openings with sizes small enough, the first inter-metal dielectric layer will fill the spaces of the openings. In contrast, for those openings with larger sizes, the glue layer is formed to cover inner surfaces of the opening conformally. In the invention, the opening exposing the first metal layer is big enough so that the glue layer is formed to cover the opening conformally without filling the opening. A chemical mechanical polishing step is performed to remove the inter-metal dielectric layer on the inter-layer dielectric layer, and the glue layer on the inner surfaces of the openings with larger sizes. A second inter-metal layer is formed on the first inter-metal layer and to fill the first openings. The second inter-metal layer is etched to form second via holes or contact window openings. Among the second openings, there is one opening exposing the first metal layer. A glue layer is formed on the second inter-metal dielectric layer and to cover a surface of the opening exposing the first metal. A second metal layer is formed and patterned on the second inter-metal dielectric layer. An over etching step is performed until the first metal layer exposed by the opening is removed. Therefore, the electrical connection between the gate and the protection structure is open and the electrical performance of the circuit is enhanced.
Both the foregoing general description and the following detailed description are exemplary and explanatory only and are not restrictive of the invention, as claimed.
REFERENCES:
patent: 6048761 (2000-04-01), En
H. Shin et al., “Impact of Plasma Charging damage and Diode Protection on Scaled Thin Oxide”, International Electron Devices Meeting 1993, IEEE Cat. No. 93CH3361-03, 1993, pp. 467-470.
Lee Tzung-Han
Wang Mu-Chun
Bowers Charles
Sarkar Asok Kumar
Thomas Kayden Horstemeyer & Risley LLP
United Microelectronics Corp.
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