Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2000-12-19
2003-09-23
Niebling, John F. (Department: 2812)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S531000
Reexamination Certificate
active
06624030
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to power semiconductor devices, and more particularly the invention relates to a power semiconductor rectifier device and a method of making same.
Power semiconductor rectifiers have a variety of applications including use in power supplies and power converters. Heretofore, Schottky diodes have been used in these applications. A Schottky diode is characterized by a low turn-on voltage, fast turnoff, and nonconductance when the diode is reverse biased. However, to create a Schottky diode a metal-silicon barrier must be formed. In order to obtain the proper characteristics for the Schottky diode, the barrier metal is likely different than the metal used in other process steps such as metal Ohmic contacts. Further, Schottky diode rectifiers suffer from problems such as high leakage current and reverse power dissipation. Also, these problems increase with temperature causing reliability problems for power supply applications. Therefore, the design of voltage converters using Schottky barrier diodes can cause designer problems for many applications.
A semiconductor power rectifier device is known which does not employ Schottky barriers.
FIG. 1
from U.S. Pat. No. 5,818,084 is a schematic of such a device which comprises a MOSFET transistor shown generally at
10
having a source/drain
12
which is shorted to a gate
14
. A parasitic diode
16
is connected from the source/drain
12
to the drain/source
18
. The patent discloses the use of a trench for accommodating the gate.
Copending application Ser. No. 09/283,537, supra, discloses a vertical semiconductor power rectifier device which employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate-to-drain short via common metallization. This provides a low V
f
path through the channel regions of the MOSFET cells to the source region on the other side of the device. The method of manufacturing the rectifier device provides highly repeatable device characteristics at reduced manufacturing costs. The active channel regions of the device are defined using pedestals in a double spacer, double implant self-aligned process. The channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations and spatial sidewall formation.
Copending application Ser. No. 09/544,730, supra, discloses an improved method of manufacturing a semiconductor power rectifier device and the resulting structure. As shown in the section view of
FIG. 2
the semiconductor substrate
20
and epitaxial layer
22
functions as one source/drain (e.g. the drain) of the device and a plurality of second source/drain (e.g. source) regions
24
are formed on a major surface of the substrate along with a plurality of gate electrodes with the source/drain and gate electrodes
26
positioned within a guard ring
28
and, optionally, conductive plugs
30
in the major surface. A conductive layer
32
contacts source/drain regions
24
and gate electrodes
26
, and conductive layer
34
contacts substrate
20
.
The semiconductive rectifier device is fabricated using conventional semiconductor processing steps including photoresist masking, plasma etching, and ion implantation in forming the guard ring, conductive plugs, source/drain regions, and gate electrodes overlying device channel regions. In accordance with one feature of the disclosed process, a photoresist mask used in defining the gate oxide and gate of the device is isotropically or otherwise etched to expose peripheral portions of the gate electrode through which ions are implanted to create channel regions in body regions under and controlled by the gate electrode.
FIG. 3
is a plan view of the device showing the boundary of substrate
20
, guard ring
28
, optional plugs
30
, and source/drains
24
in unit cells, and top electrode
32
. The P-N junction
36
between the channel region and epitaxial layer
22
of the bottom source/drain is defined by a shallow uniform Boron implant which forms p-region
38
.
SUMMARY OF THE INVENTION
The present invention is an improvement to the process and device of copending application Ser. No. 09/544,730. In particular, the P-N junction between each channel and the underlying source/drain region has a gradual slope and is less abrupt under each gate electrode as compared to the device in the copending application. This allows a more vertical flow of current from the top source/drain regions to the underlying substrate source/drain region which increases current flow at a lower turn-on voltage.
In fabricating the device, isotropic etching is used to form a sloped ion implant mask through which ions are implanted to form a laterally graded P-N junction for a channel region. The gate electrode for a unit cell overlaps the laterally graded P-N junction in the finished device.
Unlike the earlier methods which rely on spacers for allowing accurately separate dopant implant concentrations under the gate to control channel length, spacers are not required in the present invention. The invention allows a significant increase in device packing density since no space is needed between pedestals for spacers, and tighter control of dopant peak separation is realized using the sloped ion implant mask. Thus, shorter channels can be fabricated, from approximately 0.25 micron to 0.1 micron.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
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Chang Paul
Chern Geeng-Chuan
Hsueh Wayne Y. W.
Lin Charles
Rodov Vladimir
Advanced Power Devices, Inc.
Beyer Weaver & Thomas LLP
Niebling John F.
Roman Angel
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