Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-03-13
2002-07-16
Chaudhari, Chandra (Department: 2813)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S167000, C438S173000, C438S586000
Reexamination Certificate
active
06420225
ABSTRACT:
BACKGROUND OF THE INVENTION
This invention relates generally to power semiconductor devices, and more particularly the invention relates to a power semiconductor rectifier device and a method of making same.
Power semiconductor rectifiers have a variety of applications including use in power supplies and power converters. Heretofore, Schottky diodes have been used in these applications. A Schottky diode is characterized by a low turn-on voltage, fast turn-off, and nonconductance when the diode is reverse biased. However, to create a Schottky diode a metal-silicon barrier must be formed. In order to obtain proper characteristics for the Schottky diode, the barrier metal is likely different than the metal used in other process steps such as metal ohmic contacts. Further, Schottky diode rectifiers suffer from problems such as high leakage current and reverse power dissipation. Also, these problems increase with temperature causing reliability problems for power supply applications. Therefore the design of voltage converters using Schottky barrier diodes can cause design problems for many applications.
A semiconductor power rectifier device is known which does not employ Schottky barriers.
FIG. 1
from U.S. Pat. No. 5,818,084 is a schematic of such a device which comprises of a MOSFET transistor shown generally at
10
having a source/drain
12
which is shorted to a gate
14
. A parasitic diode
16
is connected from the source/drain
12
to the drain/source
18
. The patent discloses the use of a trench for accommodating the gate.
Copending application Ser. No. 09/283,537, supra, discloses a vertical semiconductor power rectifier device which employs a large number of parallel connected cells, each comprising a MOSFET structure with a gate-to-drain short via common metallization. This provides a low V
f
path through the channel regions of the MOSFET cells to the source region on the other side of the device. The method of manufacturing the rectifier device provides highly repeatable device characteristics at reduced manufacturing costs. The active channel regions of the device are defined using pedestals in a double spacer, double implant self-aligned process. The channel dimensions and doping characteristics may be precisely controlled despite inevitable process variations and spatial sidewall formation.
Copending applications Ser. No. 09/544,730 and 14987-000700US, supra disclose improved methods of manufacturing a semiconductor power rectifier device and the resulting structure. As shown in the section view of
FIG. 2
the semiconductor substrate
20
and epitaxial layer
22
functions as one source/drain (e.g. the drain) of the device and a plurality of second source/drain (e.g. source) regions
24
are formed on a major surface of the substrate along with the plurality of gate electrodes with the source/drain and gate electrodes
26
positioned within a guard ring
28
and, optionally, conductive plugs
30
in the major surface. A conductive layer
32
contacts source/drain regions
24
and gate electrodes
26
, and conductive layer
34
contacts substrate
20
.
The semiconductive rectifier device is fabricated using conventional semiconductor processing steps including photoresist masking, plasma etching, and ion implantation in forming the guard ring, conductive plug, source/drain regions, and gate electrodes overlying device channel regions. In accordance with one feature of the disclosed process, a photoresist mask is used in defining the gate oxide and gate of the device which is anisotropically or otherwise etched to expose peripheral portions of the gate electrode through which ions are implanted to create channel regions in body regions under and controlled by the gate electrode.
FIG. 3
is a plan view of the device showing the boundary of substrate
20
, guard ring
28
, optional plugs
30
and source/drains
24
in unit cells, and top electrode
32
. The P-N junction
36
between the channel region and the epitaxial layer
22
of the bottom source/drain is defined by shallow uniform boron implant which forms p-region
38
.
SUMMARY OF THE INVENTION
The present invention is an improvement to the process and device of copending application Ser. No. 09/544,730 and application Ser. No. 14987-000700US.
In one embodiment polysilicon gate processing is used, and spacers can be provided for protecting the channel region from metallization used in forming the common contact to the gates, top source/drain, and shunt diode. In another embodiment a metal gate process is provided. Spacer technology provides for process compatibility with older photo process equipment.
The invention and objects and features thereof will be more readily apparent from the following detailed description and appended claims when taken with the drawings.
REFERENCES:
patent: 4982260 (1991-01-01), Chang et al.
patent: 5430315 (1995-07-01), Rumennik
patent: 5818084 (1998-10-01), Williams et al.
patent: 5825079 (1998-10-01), Metzler et al.
patent: 5877515 (1999-03-01), Ajit
patent: 6097046 (2000-08-01), Plumton
patent: 6186408 (2001-02-01), Rodov et al.
Chang Paul
Chern Geeng-Chuan
Chiang Ching-Lang
Lin Charles
Rodov Vladimir
APD Semiconductor, Inc.
Chaudhari Chandra
Huynh Yennhu B.
Townsend and Townsend / and Crew LLP
Woodward Henry K.
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