Method of fabricating PMOS and NMOS transistor on the same...

Details Method of fabricating PMOS and NMOS transistor on the same... Method of fabricating PMOS and NMOS transistor on the same...

2011-01-18

2011-01-18

Chambliss, Alonzo (Department: 2892)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S285000, C438S479000, C257S204000, C257S288000, C257S347000, C257S616000, C257SE27046, C257SE21632

Reexamination Certificate

active

07871878

ABSTRACT:
A method of manufacturing a semiconductor device that includes a first and second device regions on a substrate. The method includes the steps of forming an insulation layer on the substrate, laminating a first semiconductor layer having a plane orientation different from the surface of the substrate on the insulation layer and exposing the substrate by removing the insulation layer and the first semiconductor layer from the second device region. A second semiconductor layer having the same plane orientation as the substrate and that is made of a strained layer is formed by epitaxial growth on the exposed substrate in the second device region.

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Japanese Patent Office, Office Action issued in Patent Application JP 2004-294562, on Oct. 27, 2009.

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