Method of fabricating nonvolatile memory device

Details Method of fabricating nonvolatile memory device Method of fabricating nonvolatile memory device

1998-01-30

2002-01-01

Chaudhuri, Olik (Department: 2814)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S262000, C438S263000, C438S264000, C438S594000

Reexamination Certificate

active

06335243

ABSTRACT:

This application claims the benefit of Korean Application No. 31837/1997 filed on Jul. 9, 1997, which is hereby incorporated by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a semiconductor device, and more particularly, to a method of fabricating a nonvolatile memory device. Although the present invention is suitable for a wide scope of applications, it is particularly suitable for fabricating a nonvolatile memory device having a minimum effective cell size.
2. Discussion of the Related Art
There are two factors determining an effective size of a memory cell: cell size itself and construction of cell array. Thus, a packing density of a nonvolatile memory device, such as an electrically erasable programmable read only memory (EEPROM) and a flash EEPROM, is limited by the effective size of the memory cell. Further, a minimum cell construction for the memory cell is a simple stacked-gate structure.
As the nonvolatile memory devices have been widely used in electronics industries, researches and developments are directed to such devices. Yet, cost-per-bit of a memory is still too expensive so that the nonvolatile semiconductor memory device can not be readily applicable for mass storage media. Further, low power consuming devices are more preferable for applications in the area of portable electronics. As a result, developments and researches for the nonvolatile memory devices have been specifically directed to reduce the cost-per-bit.
A packing density of a conventional nonvolatile memory device depends on the number of memory cells therein. On the other hand, multi-bit cells store a data of one bit or more than one bit in a memory cell, so that the packing density of the storing data can be increased without decreasing the size of the memory cell.
In order to obtain the aforementioned multi-bit cell, more than two threshold voltage levels should be programmed for each memory cell. For example, to store a data of two bits in a cell, each cell should be programmed in four threshold voltage levels (2
2
=4). The four threshold voltage levels are 00, 01, 10, and 11 in a logic state. In such multi-level programing, one of the significant problems in each threshold voltage level is the statistical distribution. For example, a value of the distribution is about 0.5 V.
Therefore, the distribution has to be reduced by adjusting each threshold voltage level. Consequently, more threshold voltage levels can be programmed and the number of bits per cell is increased. One of the ways to reduce the voltage distribution is to program the memory cell by alternately repeating programming steps and verifying steps. A series of voltage pulses are applied to the cells to program the nonvolatile memory cells to have desired threshold voltage levels. Then, a reading step is performed between the voltage pulses to verify whether or not the cells reach the desired threshold voltage levels. During each verification step, if a verified threshold voltage level value reaches the threshold voltage level, the programming is completed.
However, it is difficult to reduce the error distribution in threshold voltage levels by adjusting a finite program voltage pulse width in the aforementioned method. Further, since algorithm circuit alternately repeats programming and verifying steps, a peripheral circuit area in the device is increased and an operation period becomes too long.
FIGS. 1A and 1B
are a schematic diagram and a crosssectional view of a conventional nonvolatile memory device having a simple stacked-gate structure, respectively.
As shown in
FIG. 1B
, a floating gate
3
and a tunneling oxide layer
2
are successively formed on a p-type semiconductor substrate
1
. A dielectric layer
4
is formed and a control gate
5
are formed on the floating gate
3
. N-type source and drain regions
6
a
and
6
b
are formed below the surface of the semiconductor substrate
1
at both sides of the floating gate
3
.
In such nonvolatile memory device having the aforementioned structure, an effective cell size is inevitably small. Generally, the shorter the effective cell size, the lower the coupling constant. As a result, a coupling constant for the control gate
5
is low. Accordingly, in order to improve a low coupling constant, a dielectric layer
4
(for example, oxide nitride oxide) is formed between the floating gate
3
and the control gate
5
. However, complex processes including an annealing at a high temperature is required to form the dielectric layer
4
.
Referring to
FIG. 1A
, each nonvolatile memory cell includes a floating gate
3
, a control gate
5
for adjusting charges provided in the floating gate
3
, and an electric field effect transistor for reading or verifying the amount of charge carriers provided in the floating gate
3
during programming. More specifically, the electric field transistors includes a floating gate
3
, a source
6
a
, a drain
6
b
, and a channel region
7
formed between the source and drain
6
a
and
6
b.
When a voltage applied to the control gate
5
and the drain
6
b
is high enough to perform programming, a current flows between the drain
6
b
and the source
6
a
. If the current is the same as or smaller than a reference current, a programming completion signal is generated.
A conventional nonvolatile memory device will be described with reference to the accompanying drawings.
FIG. 2
is a circuit diagram of a conventional nonvolatile memory device. As shown in
FIG. 2
, a plurality of metal bit lines
209
are formed to be spaced apart from one another by a predetermined distance in a column direction. A plurality of word lines
210
are formed to be perpendicular to the metal bit lines
209
. A common source line
211
per two word lines
210
is formed in parallel with the word lines
210
.
The drains
6
b
shown in
FIG. 1A
are connected to the metal bit lines
209
and the sources
6
a
are connected to the common source lines
211
. Thus, one metal contact hole
208
per two cells is required, so that an effective size of the memory cells become larger taking in consideration of the metal contact holes
208
. In other words, as previously described in
FIG. 1B
, the conventional nonvolatile memory device has a simple stacked-gate structure to minimize the cell size. The effective size, however, is limited by a pitch of the metal contact holes
208
.
To solve this problem, the metal contact holes are eliminated in an array of the memory cell. Thus, the array of the cell employs a simple stacked-gate structure without the metal contact holes to minimize the effective cell size. Nonetheless, a program disturbance occurs in a deselected cell adjacent to a direction of the word lines.
FIG. 3
illustrates another conventional nonvolatile memory device using split-channel cells to have an asymmetry structure where selection gates
312
are formed. In this device, the problem of a simple stacked-gate structure cell can be solved because the program disturbance and over-erasure are eliminated in programming by a hot electron injection.
The nonvolatile memory device shown in
FIG. 3
includes a plurality of word lines
310
formed on a semiconductor substrate (not shown) separated from one another by a predetermined distance, bit lines
313
formed to be perpendicular to the word lines
310
to form a plurality of squares, and a plurality of nonvolatile memory cells disposed as a square.
Each nonvolatile memory cell shown in
FIG. 3
includes a floating gate
3
, as shown in
FIG. 1A
, a control gate
5
for adjusting the amount of charge provided for the floating gate
3
in programming, and an electric field effect transistor for reading or verifying the amount of charge carriers provided for the floating gate
3
during programming. Specifically, the electric field effect transistor includes a floating gate
3
, a source
6
a
, a drain
6
b
, and a channel region
7
formed between the drain and source
6
a
and
6
b.
A control gate
5
of each nonvolatile memory cell is connected to the adjacent

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