Method of fabricating non-volatile memory cell adapted for...

Details Method of fabricating non-volatile memory cell adapted for... Method of fabricating non-volatile memory cell adapted for...

2006-05-23

2006-05-23

Fourson, George (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S221000, C438S276000, C438S287000

Reexamination Certificate

active

07049189

ABSTRACT:
A method of manufacturing a non-volatile memory cell includes forming a bottom dielectric layer and a charge trapping layer on a substrate sequentially. The electron trapping layer is patterned to form a trench exposing a portion of the bottom dielectric layer. A top dielectric layer is formed over the substrate and covers the electron trapping layer and the exposed bottom dielectric layer. A conductive layer is then formed on the top dielectric layer. The conductive layer, the top dielectric layer, the electron trapping layer and the bottom dielectric layer are patterned to form a stacked structure, wherein a width of the stacked structure is larger than a width of the trench. A source/drain region is formed in the substrate adjacent to the edges of the stacked structure. Because the electron trapping layer of the memory cell is divided into two isolation structures according to the invention, it is adapted for the integration of devices and for long-time operation.

REFERENCES:
patent: 6538292 (2003-03-01), Chang et al.
patent: 6639271 (2003-10-01), Zheng et al.
patent: 6835621 (2004-12-01), Yoo et al.
Wolf, Stanley; Process Integration for the VLSI Era vol. 2: Process Integration; p. 354; Lattice Press, 1990; Sunset Beach, CA.

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