Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having junction gate
Reexamination Certificate
2007-10-23
2007-10-23
Cao, Phat X. (Department: 2814)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having junction gate
C438S279000, C257SE21638
Reexamination Certificate
active
11306248
ABSTRACT:
A method of fabricating non-volatile memory is provided. A plurality of first memory cells is formed on the memory cell region of a substrate. Each first memory cell includes a first composite layer, a first gate and a cap layer. There is a gap between two adjacent first memory cells. Then, a plurality of gates is formed in the respective gaps. The gates together with a second composite layer form a plurality of second memory cells. The second memory cells and the first memory cells together constitute a memory cell column. In the meantime, a plurality of gate structures is also formed on the peripheral circuit region. The gates in the gaps and the gates in the peripheral circuit region are formed using the same conductive layers.
REFERENCES:
patent: 4939690 (1990-07-01), Momodomi et al.
patent: 5930631 (1999-07-01), Wang et al.
patent: 2004/0121548 (2004-06-01), Fishburn et al.
patent: 2006/0220097 (2006-10-01), Ogura
Pittikoun Saysamone
Tseng Wei-Chung
Wei Houng-Chi
Cao Phat X.
Jiang Chyun IP Office
Powerchip Semiconductor Corp.
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