Method of fabricating MOS transistor having shallow...

Details Method of fabricating MOS transistor having shallow... Method of fabricating MOS transistor having shallow...

2002-04-05

2003-09-16

Niebling, John F. (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S301000, C438S229000

Reexamination Certificate

active

06620668

ABSTRACT:

BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a method of fabricating a MOS transistor, and more particularly, to a method of a MOS transistor having shallow source/drain junction regions.
2. Description of the Related Art
In general, gate patterns composed of gate oxide layers and gate electrodes are formed on a semiconductor substrate. Source/drain junction regions are formed in the semiconductor substrate underneath both sidewalls of the gate patterns. As a result, MOS transistors are formed.
The source/drain junction regions must be shallow junction regions as the MOS transistors are highly integrated. The shallow junction regions must be junction regions, which are formed to a shallow depth into a substrate, have a high concentration and high activation rate of impurities to reduce resistance, and has an abrupt junction profile in horizontal and vertical directions.
Conventional source/drain junction regions are formed by an ion implantation method or a solid phase diffusion method. In the ion implantation method, an ion implanter highly accelerates impurities with a high acceleration voltage and then implants the impurities into a substrate to form source/drain junction regions. In the solid phase diffusion method, a solid phase diffused source is formed on a substrate, and then a dopant in the solid phase diffusion source is diffused and doped into the substrate to form shallow junction regions.
In order to avoid the confusion of the terminology used in this detailed description of the present invention, impurities implanted by the ion implantation method are described as “impurities”, and impurities implanted by the solid phase diffusion method are described as “dopant”. Also, implanting ionic impurities is referred to as “ion implantation”, and diffusing impurities of a substrate already containing impurities by the solid phase diffusion method is referred to as “doping”.
The ion implantation method damages the crystal structure of the substrate because of the kinetic energy of impurity ions, and thus dislocation occurs. The dislocation causes a sharp diffusion of the implanted impurities as well as leakage in source/drain junction regions. Thus, it becomes impossible to form shallow source/drain junction regions. The solid phase diffusion method has difficulty increasing the doping concentration of dopant in the solid phase diffusion source sufficient for shallow source/drain junction regions having a low resistance. Also, there is a problem of precisely controlling the doping concentration of the dopant in the solid phase diffusion source.
SUMMARY OF THE INVENTION
To solve the above-described problems, it is an object of the present invention to provide a method of fabricating a MOS transistor having shallow source/drain junction regions in which dislocation does not occur and the doping concentration of impurities is precisely controlled.
Accordingly, to achieve the above object, according to an embodiment of the present invention, there is provided a method of fabricating a MOS transistor. In the method, gate patterns are formed on a semiconductor substrate and a diffusion source layer is on the entire surface of the semiconductor substrate. The diffusion source layer may be an USG layer or a silicon oxide layer. The USG layer may be formed by spin-coating and densifying a liquid silicate glass. The silicon oxide layer may be formed by CVD or PECVD using a compound gas containing SiH
4
and O
2
, dry oxidation, or wet oxidation. The whole of the diffusion source layer or a portion of the diffusion source layer may be etched to be thin.
The same type or different type of impurities are implanted into the diffusion source layer several times in different directions so that the impurity concentration of portions of the diffusion source layer on upper surfaces of the gate patterns and the semiconductor substrate is higher than the impurity concentration of portions of the diffusion source layer on sidewalls of the gate patterns due to a shadow effect. The implantation of the impurities into the diffusion source layer may be performed using a general ion implanter or a plasma ion implanter including a Pill and an ISI. The impurities may be implanted into the diffusion source layer at an angle from the semiconductor substrate to adjust the impurity concentration of the portions of the diffusion source layer on the sidewalls of the gate patterns to 10
17
-10
22
cm
−3
. The impurities may be implanted vertically into the diffusion source layer to adjust the impurity concentration of the portions of the diffusion source layer on the upper surfaces of the gate patterns and the semiconductor substrate to 10
18
-10
22
cm
−3
.
Impurities contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions underneath the sidewalls of the gate patterns and highly doped source/drain regions by a self-alignment method. Forming the shallow source/drain junction regions by the solid phase diffusion method may be performed using RTA, spike annealing, or laser annealing. It is preferable that in the RTA, the semiconductor substrate on which the diffusion source layer containing the impurities is formed is annealed at a temperature of 950-1150° C. for 1-1000 seconds in an inert gas atmosphere. It is preferable that in the spike annealing, the semiconductor substrate on which the diffusion source layer containing the impurities is formed is annealed at a temperature of 950-1200° C. in an inert gas atmosphere. Preferably, the shallow source/drain junction regions have a doping depth of 50 nm or less on the semiconductor substrate and a doping concentration 10
18
-10
22
cm
−3
.
According to another embodiment of the present invention, there is provided a method of fabricating a MOS transistor. In the method, gate patterns are formed on a semiconductor substrate in which a P-well and an N-well are formed. A diffusion source layer is formed on the entire surface of the semiconductor substrate. A photoresist pattern is formed on the diffusion source layer to open the N-well or the P-well. The same type or different type of impurities are implanted first into a portion of the diffusion source layer over the N-well and then into a portion of the diffusion source layer over the P-well, or first into the portion of the diffusion source layer over the P-well and then into the portion of the diffusion source layer over the N-well, several times in different directions so that the impurity concentration of portions of the diffusion source layer on upper surfaces of the gate patterns and the semiconductor substrate is higher than the impurity concentration of portions of the diffusion source layer at sidewalls of the gate patterns due to a shadow effect. The photoresist pattern is removed. Impurities contained in the portions of the diffusion source layer over the N-well and the P-well are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD regions underneath the sidewalls of the gate patterns and highly doped source/drain regions by a self-alignment method.
As described above, according to the present invention, the same type or different type of impurities are implanted into the diffusion source layer several times in different directions. As a result, dislocation does not occur and the impurity concentration of the diffusion source layer can be nonuniformly controlled. Also, the impurities nonuniformly contained in the diffusion source layer are diffused into the semiconductor substrate by a solid phase diffusion method to form shallow source/drain junction regions having LDD/SDE regions and highly doped source/drain regions by a self-alignment method.


REFERENCES:
patent: 4965220 (1990-10-01), Iwasaki
patent: 5340770 (1994-08-01), Allman et al.
patent: 5407847 (1995-04-01), Hayden et al.
patent: 5478776 (1995-12-01), Luftman et al.
patent:

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