Method of fabricating MOS transistor having fully silicided...

Details Method of fabricating MOS transistor having fully silicided... Method of fabricating MOS transistor having fully silicided...

2007-02-20

2007-02-20

Lebentritt, Michael (Department: 2812)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S299000, C438S233000, C438S243000, C438S291000, C438S303000, C438S529000, C438S592000, C438S626000, C438S682000, C257SE21199, C257SE21426, C257SE21443, C257SE21444, C257SE21636

Reexamination Certificate

active

11065242

ABSTRACT:
There is provided a method of fabricating a MOS transistor having a fully silicided gate, including forming a gate pattern and gate spacers on a semiconductor substrate, the gate pattern including a lower gate pattern, an insulating layer pattern, and an upper gate pattern, which are sequentially stacked. Source/drain regions are formed by implanting impurity ions into an active region using the gate pattern and the gate spacers as ion implantation masks. Then, a protecting layer is formed on the semiconductor substrate having the gate pattern, and the protecting layer is planarized until the upper gate pattern is exposed. Then, by removing the exposed upper gate pattern and the insulating layer pattern, the lower gate pattern is exposed. Then, the protecting layer is selectively removed, thereby exposing the source/drain regions. The exposed lower gate pattern is fully converted to a gate silicide layer, and a silicide layer is concurrently formed on the surfaces of the source/drain regions.

REFERENCES:
patent: 5981365 (1999-11-01), Cheek et al.
patent: 5994193 (1999-11-01), Gardner et al.
patent: 6080648 (2000-06-01), Nagashima
patent: 6096642 (2000-08-01), Wu
patent: 11-284179 (1999-10-01), None
patent: 01-26811 (2001-04-01), None
“Totally Silicided (CoSi2)Polysilicon: a novel approach to very low-resistive gate(˜2Ω/□)without metal CMP nor etching,” B. Tavel, et al., 2001 IEEE.

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