Method of fabricating MOS transistor having a P.sup.+ -polysilic

Details Method of fabricating MOS transistor having a P.sup.+ -polysilic Method of fabricating MOS transistor having a P.sup.+ -polysilic

1996-07-29

1999-03-16

Bowers, Charles

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

H01L 21336, H01L 218234

Patent

active

058829628

ABSTRACT:
A method of forming a MOS transistor having a p.sup.+ -polysilicon gate includes doping an amorphous silicon layer with phosphorus, thereby forming a n.sup.- amorphous silicon layer atop of a gate oxide. The n.sup.- amorphous silicon layer is then doped with boron to convert the n.sup.- amorphous silicon layer into a p.sup.+ -amorphous silicon layer. The p.sup.+ -amorphous silicon layer is then thermally treated to convert the p.sup.+ -amorphous silicon layer into a p.sup.+ -polysilicon layer. The p.sup.+ -polysilicon layer is then patterned into a gate for a MOS transistor. The phosphorus ions in the p.sup.+ -polysilicon help to fix the boron ions in the polysilicon gate, thereby reducing the diffusion of the boron ions and penetration of boron into the gate oxide.

REFERENCES:
patent: 4637836 (1987-01-01), Flatley et al.
patent: 5464789 (1995-11-01), Saito

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