Semiconductor device manufacturing: process – Making field effect device having pair of active regions... – Having insulated gate
Reexamination Certificate
2001-01-12
2003-02-11
Lee, Eddie (Department: 2815)
Semiconductor device manufacturing: process
Making field effect device having pair of active regions...
Having insulated gate
C438S211000, C438S257000, C438S261000, C438S265000
Reexamination Certificate
active
06518110
ABSTRACT:
FIELD OF THE INVENTION
The present invention relates to a memory cell structure of a flash memory and a method for fabricating the same and, more particularly, to a flash memory having annular floating gates. The present invention uses the capacitance coupling between the source and the floating gate to form a channel in the substrate under the floating gate. Hot electrons are injected into the floating gate or released from the floating gate to the control gate through inerpoly dieletric by injection point on the top of floating gate.
BACKGROUND OF THE INVENTION
Flash memories have been widely used in electronic products such as portable computers or communication apparatuses because of their non-volatile functions of electrically writing and erasing. Flash memories can generally be categorized into two types according to the shape of their gates: the stacked gate type and the split gate type.
FIG. 1
shows a cross-sectional view of a memory cell of a flash memory of stacked gate type in prior art. As shown in the figure, a stacked gate is formed on a semiconductor substrate
11
. The stacked gate comprises from bottom to top a gate oxide
13
, a floating gate
15
, an interpoly dielectric
17
, and a control gate
19
. A drain region
12
and a source region
14
are formed in the substrate
11
respectively at one side of the stacked gate by ion implantation. Through applied voltage between the control gate
19
and the drain
12
and the source
14
, a channel and hot electrons can be formed in the substrate
11
under the floating gate
15
. These hot electrons are injected from the drain
12
through the gate oxide
13
into the floating gate
15
by means of hot electron injection so as to complete a program process of writing data. Contrarily, electrons are released from the floating gate
15
to the source
14
by means of the Fowler-Nordheim (FN) tunneling effect for erasing data.
However, for a flash memory of stacked gate type, it is difficult to control the number of electrons released from the floating gate
15
during the data-erasing procedure. Over erase may easily arise, deteriorating the quality and reliability of the flash memory.
Therefore, flash memories of split gate type have been developed. As shown in
FIG. 2
, a thinner oxide (such as a tunneling oxide)
23
, a floating gate
25
, a dielectric film
271
, and a control gate
29
are successively deposited on a semiconductor substrate
21
. Next, a source region
22
and a drain region
24
are formed at proper positions in the substrate
21
by ion implantation. One end of the control gate
29
has a selecting gate part
295
extending to the drain
24
. A selecting gate oxide
275
is disposed between the selecting gate part
295
of the control gate
29
and the drain
24
.
Flash memories of split gate type can effectively solve the problem of over erase occurring easily in flash memories of stacked gate type. However, the length of the selecting gate part
295
has a certain limit. Leakage current will be generated if its length is reduced. Moreover, it is difficult to align the relative positions of the source
22
, the drain
24
, the control gate
29
, and the floating gate. The lengths of the selecting gate part
295
and the floating gate
25
thus can not be effectively reduced. Additionally, to enhance the efficiencies of writing and erasing data, larger memory cell size is needed to achieve high capacitance coupling ratio. Therefore, the area of memory cell thereof will be large so that integration density of memory cell can not be effectively increased.
Additionally, although a thinner tunneling oxide can enhance the tunneling effect of electrons, it is very difficult to fabricate a thin oxide having high tunneling effect of electrons in low-power non-volatile memory devices. Moreover, leakage current resulted from increased defect density and stress defects may easily arise to deteriorate the reliability of devices.
SUMMARY AND OBJECTS OF THE PRESENT INVENTION
The primary object of the present invention is to provide a flash memory structure and a method for fabricating the same. In the proposed flash memory, an annular floating gate situated between the drain and the source is exploited. An interpoly dielectric and a control gate are stacked on the surface of the floating gate and on the gate oxide exposed at the center of the floating gate by means of self-alignment. Thereby above mentioned problem can be overcome, and reliability of devices can be enhanced.
Another object of the present invention is to provide a flash memory structure and a method for fabricating the same. In the proposed flash memory, an interpoly dielectric and a control gate circumvent the periphery of the floating gate to enhance the capacitance coupling ratio between the control gate, the floating gate, and the source. Memory cells of the flash memory having efficient program process of writing or erase process can thus be obtained.
Yet another object of the present invention is to provide a flash memory structure and a method for fabricating the same. In the proposed flash memory, the interpoly dielectric circumventing the floating gate is an oxide
itride/oxide (ONO) structure or an oxide
itride (ON) structure. The quality and thickness of the interpoly dielectric can be exactly controlled. Flash memory cells of high capacitance coupling ratio and low leakage current can thus be produced.
Yet another object of the present invention is to provide a flash memory structure and a method for fabricating the same. In the proposed flash memory, the floating gate and the source and the drain are electrically insulated by a thicker oxide to reduce accuracy requirement of the fabrication process and to enhance reliability of devices.
Yet another object of the present invention is to provide a flash memory structure and a method for fabricating the same. The proposed fabrication method is compatible to the general fabrication process of CMOS devices, thus simplifying the fabrication process.
Still yet another object of the present invention is to provide a flash memory structure and a method for fabricating the same. In the proposed flash memory, an injection point not covered by a silicon nitride (SiN) film is formed on the top of the floating gate to displace the electrons in the floating gate to the passage of the control gate.
To accomplish above objects, the present invention proposes a memory cell structure of a flash memory. The proposed memory cell structure comprises mainly a semiconductor substrate, an annular floating gate, a first oxide film, a SiN film and a control gate. A source and a drain are formed in the substrate. Part region of the floating gate covers on the surfaces of the source and the drain. A gate oxide electrically insulates the floating gate and the source and the drain. The substrate exposes at the center of the floating gate. The first oxide film covers on the surface of the floating gate and the surface of the substrate exposed at the center and the periphery of the floating gate. The SiN film is situated on the surface of the first oxide adjacent to the floating gate. An injection point not covered by the SiN film is disposed on the top of the floating gate. The control gate covers on the surface of a second oxide.
The present invention also provides a method for fabricating a memory cell structure of a flash memory. The proposed fabrication method comprises the following steps: providing a semiconductor substrate; forming a pad oxide and a SiN on the surface of the substrate; forming a plurality of field oxides in the substrate by the photolithography, etching, and oxidation techniques; etching out the patterns of the pad oxide and the SiN to reserve only the part of the SiN situated between two field oxides by the photolithography and etching techniques; forming a gate oxide on the uncovered surface of the substrate; forming a first poly-silicon on the surface of the SiN and the gate oxide; etching out the pattern of the first poly-silicon by anisotropic dry etching techniques to form
Brock II Paul E
Lee Eddie
LandOfFree
Method of fabricating memory cell structure of flash memory... does not yet have a rating. At this time, there are no reviews or comments for this patent.
If you have personal experience with Method of fabricating memory cell structure of flash memory..., we encourage you to share that experience with our LandOfFree.com community. Your opinion is very important and Method of fabricating memory cell structure of flash memory... will most certainly appreciate the feedback.
Profile ID: LFUS-PAI-O-3179653