Method of fabricating memory cell in semiconductor device

Details Method of fabricating memory cell in semiconductor device Method of fabricating memory cell in semiconductor device

2006-02-07

2006-02-07

Dang, Trung (Department: 2823)

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

C438S263000, C438S264000

Reexamination Certificate

active

06995063

ABSTRACT:
A method of fabricating a memory cell in a semiconductor device, by which a data storage function is dichotomized in a manner of controlling a quantity of electrons injected in each floating gate according to drain and control gate voltages applied thereto. The method includes the steps of defining source, first floating gate, control gate, second floating gate, and drain areas on a substrate to have the control gate area lie between the first and second floating gate areas, forming source and drain regions on the source and drain areas of the substrate, respectively, forming a gate oxide layer on the semiconductor substrate, and reducing the gate oxide layer on the first and second floating gate areas in thickness. The method also includes forming first and second floating gates on the reduced gate oxide layer in the first and second gate areas, respectively, forming an ONO layer on top sides and confronting sidewalls of the first and second floating gates, and forming a control gate on the ONO layer and the gate oxide layer on the control gate area to be overlapped with the first and second floating gates.

REFERENCES:
patent: 6518110 (2003-02-01), Wen
patent: 6903405 (2005-06-01), Takahashi
patent: 2002/0052079 (2002-05-01), Wen

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