Method of fabricating mask ROM using junction isolation

Details Method of fabricating mask ROM using junction isolation Method of fabricating mask ROM using junction isolation

1997-03-26

1999-04-06

Chaudhani, Chandra

Semiconductor device manufacturing: process

Making field effect device having pair of active regions...

Having insulated gate

438291, 438420, H01L 218246

Patent

active

058917802

ABSTRACT:
A semiconductor device comprises a semiconductor substrate formed with at least one well containing impurity ions of either a first conductivity type or a second conductivity type; a plurality of transistors each having a gate insulation film formed on the well, a gate electrode formed on the gate insulation film and a pair of diffusion layers formed in the well; and an outer diffusion layer of the same conductivity type as that of the well and self-aligned with each of the diffusion layers in an outer periphery thereof within the well; the outer diffusion layer having an impurity concentration sufficient to provide a desired junction withstand voltage and having substantially the same width as that of a depletion layer to be generated when an operational voltage is applied to the corresponding transistor; the impurity of the well being set for a concentration such that a threshold voltage of a parasitic transistor appearing below the gate electrode connecting adjacent transistors is higher than a power supply voltage, whereby the adjacent transistors are isolated from each other.

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